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U.S. Patents Awarded to Inventors in California (Feb. 8)
(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service
Targeted News Service
ALEXANDRIA, Va., Feb. 8 -- The following federal patents were awarded to inventors in California.
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Miramar Labs Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Miramar Labs, Sunnyvale, Calif., has been assigned a patent (8,367,959) developed by Robert Bruce Spertell, Northridge, Calif., for a "method and apparatus for treating subcutaneous histological features."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method for treating subcutaneous histological features without affecting adjacent tissues adversely employs microwave energy of selected power, frequency and duration to penetrate subcutaneous tissue and heat target areas with optimum doses to permanently affect the undesirable features. The frequency chosen preferentially interacts with the target as opposed to adjacent tissue, and the microwave energy is delivered as a short pulse causing minimal discomfort and side effects. By distributing microwave energy at the skin over an area and adjusting power and frequency, different conditions, such as hirsuitism and telangiectasia, can be effectively treated."
The patent application was filed on Oct. 24, 2011 (13/280,032). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,367,959&OS=8,367,959&RS=8,367,959
Written by Arpi Sharma; edited by Anand Kumar.
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Qnovo Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Qnovo, Newark, Calif., has been assigned a patent (8,368,357) developed by Dania Ghantous, Walnut Creek, Calif., Fred Berkowitz, Los Gatos, Calif., and Nadim Maluf, Los Altos, Calif., for a "method and circuitry to adaptively charge a battery/cell."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present inventions, in one aspect, are directed to techniques and/or circuitry to adapt the charging of a battery/cell using data which is representative of an overpotential of the battery/cell. In yet another aspect the present inventions are directed to techniques and/or circuitry to calculate data which is representative of an overpotential of the battery/cell."
The patent application was filed on Oct. 12, 2011 (13/271,910). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,357&OS=8,368,357&RS=8,368,357
Written by Arpi Sharma; edited by Anand Kumar.
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Arcus Technology Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Arcus Technology, Livermore, Calif., has been assigned a patent (8,368,257) developed by Christopher C. Chang, Brentwood, Calif., for an "integrated linear brushless DC motor."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A linear brushless DC motor uses a movable coil assembly, which includes at least one coil, an amplifier and a motor controller, that is configured to move relative to a stationary base assembly. The coil, the amplifier and the motor controller are assembled so that the coil, the amplifier and the motor controller are collectively displaced when the movable coil assembly is moved relative to the stationary base assembly."
The patent application was filed on Oct. 23, 2009 (12/604,975). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,257&OS=8,368,257&RS=8,368,257
Written by Arpi Sharma; edited by Anand Kumar.
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Volterra Semiconductor Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Volterra Semiconductor, Fremont, Calif., has been assigned a patent (8,368,212) developed by Ilija Jergovic, Palo Alto, Calif., and Efren M. Lacap, Union City, Calif., for a "semiconductor package with under bump metallization routing."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A semiconductor package includes a semiconductor substrate a semiconductor substrate having source and drain regions formed therein, an intermediate routing structure to provide electrical interconnects to the source and drain regions, a dielectric layer formed over the intermediate routing structure, and an under-bump-metallization (UBM) stack. The intermediate routing structure includes an outermost conductive layer, and the dielectric layer has an opening positioned over a portion of the intermediate layer routing structure. The UBM stack includes a conductive base layer formed over the dielectric layer and electrically connected to the outermost conductive layer through the opening, and a thick conductive layer formed on the base layer. A conductive bump is positioned on the UBM stack and laterally spaced from the opening."
The patent application was filed on July 27, 2011 (13/192,303). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,212&OS=8,368,212&RS=8,368,212
Written by Arpi Sharma; edited by Anand Kumar.
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Jammit Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Jammit, Hollywood, Calif., has been assigned a patent (8,367,923) developed by Scott Humphrey, Hollywood, Calif., for a "system for separating and mixing audio tracks within an original, multi-track recording."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The teachings described herein are generally directed to a system, method, and apparatus for learning music through an educational audio track embodied on a computer readable medium. The system can comprise components including a processor, an input device, a database, a transformation module, an emulation recording module, an integration engine, an output module, and an output device, wherein each component is operable in itself to perform it's function in the system and operable with other system components to provide a system to a user for learning music."
The patent application was filed on May 23, 2011 (13/113,999). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,367,923&OS=8,367,923&RS=8,367,923
Written by Arpi Sharma; edited by Anand Kumar.
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Advanced Micro Devices, Spansion Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Advanced Micro Devices, Sunnyvale, Calif., and Spansion, Sunnyvale, Calif., have been assigned a patent (8,368,219) developed by eight co-inventors for a "buried silicide local interconnect with sidewall spacers and method for making the same." The co-inventors are Arvind Halliyal, Cupertino, Calif., Zoran Krivokapic, Santa Clara, Calif., Matthew S. Buynoski, Palo Alto, Calif., Nicholas H. Tripsas, San Jose, Calif., Minh Van Ngo, Freemont, Calif., Mark T. Ramsbey, Sunnyvale, Calif., Jeffrey A. Shields, Sunnyvale, Calif., and Jusuke Ogura, Tokyo.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A buried local interconnect and method of forming the same counterdopes a region of a doped substrate to form a counterdoped isolation region. A hardmask is formed and patterned on the doped substrate, with a recess being etched through the patterned hardmask into the counterdoped region. Dielectric spacers are formed on the sidewalls of the recess, with a portion of the bottom of the recess being exposed. A metal is then deposited in the recess and reacted to form silicide at the bottom of the recess. The recess is filled with fill material, which is polished. The hardmask is then removed to form a silicide buried local interconnect."
The patent application was filed on Oct. 26, 2011 (13/281,491). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,219&OS=8,368,219&RS=8,368,219
Written by Arpi Sharma; edited by Anand Kumar.
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Lawrence Livermore National Security, University of California Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Lawrence Livermore National Security, Livermore, Calif., and the University of California, Oakland, Calif., have been assigned a patent (8,367,976) developed by Neil Reginald Beer, Pleasanton, Calif., and Ian Kennedy, Davis, Calif., for a "laser heating of aqueous samples on a micro-optical-electro-mechanical system."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system of heating a sample on a microchip includes the steps of providing a microchannel flow channel in the microchip; positioning the sample within the microchannel flow channel, providing a laser that directs a laser beam onto the sample for heating the sample; providing the microchannel flow channel with a wall section that receives the laser beam and enables the laser beam to pass through wall section of the microchannel flow channel without being appreciably heated by the laser beam; and providing a carrier fluid in the microchannel flow channel that moves the sample in the microchannel flow channel wherein the carrier fluid is not appreciably heated by the laser beam."
The patent application was filed on Dec. 10, 2008 (12/331,487). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,367,976&OS=8,367,976&RS=8,367,976
Written by Arpi Sharma; edited by Anand Kumar.
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Apple Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Apple, Cupertino, Calif., has been assigned a patent (8,367,958) developed by Adam D. Mittleman, San Francisco, Robert Scritzky, Sunnyvale, Calif., and Bradley Hamel, Sunnyvale, Calif., for a "button assembly with inverted dome switch."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A portable electronic device may have an inverted dome switch assembly. The switch assembly may have an inverted dome that has a base and a conductive underside. The base may be attached to a button member. Two electrical contacts in the button member may face the conductive underside. Corresponding conductive traces may be connected to the contacts. The dome may bear against a housing member. The button member may be movable with respect to the housing member from an unactuated position to an actuated position. The dome switch may form a footprint based upon the dome base area. The housing member may extend into a portion of the footprint and not into the remaining portion of the footprint allowing that space to be otherwise utilized."
The patent application was filed on Feb. 17, 2011 (13/029,928). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,367,958&OS=8,367,958&RS=8,367,958
Written by Arpi Sharma; edited by Anand Kumar.
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Applied Materials Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Applied Materials, Santa Clara, Calif., has been assigned a patent (8,367,924) developed by Peter Borden, San Mateo, Calif., and Li Xu, Santa Clara, Calif., for a "buried insulator isolation for solar cell contacts."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention relates to methods and apparatuses for providing a buried insulator isolation for solar cell contacts. According to certain aspects, the invention places a buried oxide under the emitter of a polysilicon emitter solar cell. The oxide provides an excellent passivation layer over most of the surface. Holes in the oxide provide contact areas, increasing the current density to enhance efficiency. The oxide isolates the contacts from the substrate, achieving the advantage of a selective emitter structure without requiring deep diffusions. The oxide further enables use of screen printing on advanced shallow emitter cells. Positioning of the grid lines close to the openings also enables use of a very thin emitter to maximize blue response."
The patent application was filed on Jan. 27, 2009 (12/360,814). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,367,924&OS=8,367,924&RS=8,367,924
Written by Arpi Sharma; edited by Anand Kumar.
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Applied Materials Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Applied Materials, Santa Clara, Calif., has been assigned a patent (8,367,983) developed by four co-inventors for an "apparatus including heating source reflective filter for pyrometry." The co-inventors are Joseph M. Ranish, San Jose, Calif., Aaron M. Hunter, Santa Cruz, Calif., Blake R. Koelmel, Mountain View, Calif., and Bruce E. Adams, Portland, Ore.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and apparatus for processing substrates and measuring the temperature using radiation pyrometry are disclosed. A reflective layer is provided on a window of a processing chamber. A radiation source providing radiation in a first range of wavelengths heats the substrate, the substrate being transparent to radiation in a second range of wavelengths within the first range of wavelengths for a predetermined temperature range. Radiation within the second range of wavelength is reflected by the reflective layer."
The patent application was filed on June 12, 2009 (12/483,770). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,367,983&OS=8,367,983&RS=8,367,983
Written by Arpi Sharma; edited by Anand Kumar.
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International Rectifier Assigned Patent for Wafer Scale Package for High Power Devices
ALEXANDRIA, Va., Feb. 8 -- International Rectifier, El Segundo, Calif., has been assigned a patent (8,368,210) developed by Henning M. Hauenstein, Redondo Beach, Calif., for a "wafer scale package for high power devices."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A semiconductor device package is formed of DBC in which thinned MOSgated and/or diode die are soldered to the bottom of an etched depression in the upper conductive layer. A via in the insulation layer of the DBC is filled with a conductive material to form a resistive shunt. Plural packages may be formed in a DBC card and may be separated individually or in clusters. The individual packages are mounted in various arrays on a support DBC board and heat sink. Integrated circuits may be mounted on the assembly and connected to the die for control of the die conduction."
The patent application was filed on Sept. 6, 2011 (13/225,987). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,210&OS=8,368,210&RS=8,368,210
Written by Arpi Sharma; edited by Anand Kumar.
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Apple Assigned Patent for Method and Apparatus for Improved Cooling Fans
ALEXANDRIA, Va., Feb. 8 -- Apple, Cupertino, Calif., has been assigned a patent (8,368,329) developed by John M. Depew, Sunnyvale, Calif., Mike Culbert, Monte Sereno, Calif., and Keith Cox, Campbell, Calif., for a "method and apparatus for improved cooling fans."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and apparatuses for improving cooling fan operation are disclosed. In one embodiment, a cooling fan's speed is maximized by adjusting a PWM signal driving the fan to change the switching point of the fan motor. In another embodiment, a method for starting a low speed cooling fan by incrementally increasing the amplitude of the PWM signal applied to the fan is disclosed. In a further embodiment, a method for controlling a fan and a fan sensor is disclosed. In this embodiment, a PWM signal is generated, a fan is driven using the PWM signal, a cycle of the PWM signal is modified, and the fan sensors is driven using the PWM signal during the cycle. In a further embodiment, a fan incorporating these improvements is disclosed."
The patent application was filed on Sept. 11, 2003 (10/661,737). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,329&OS=8,368,329&RS=8,368,329
Written by Arpi Sharma; edited by Anand Kumar.
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Oracle America Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Oracle America, Redwood City, Calif., has been assigned a patent (8,368,205) developed by four co-inventors for a "metallic thermal joint for high power density chips." The co-inventors are Seshasayee Ankireddi, Redwood City, Calif., Vadim Gektin, Redwood City, Calif., James A. Jones, Redwood City, Calif., and Margaret B. Stern, Redwood City, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for the assembly of a semiconductor package that includes cleaning a surface of a chip and a surface of a heat removal device by reverse sputtering is given. The method includes sequentially coating the surface of the chip and the surface of the heat removal device with an adhesive layer, a barrier layer, and a protective layer over a target joining area. The chip and the heat removal device are placed into carrier fixtures and preheated to a target temperature. Then a metallic thermal interface material (TIM) preform is mechanically rolled onto the surface of the chip and the first and the second carrier fixtures are attached together such that the metallic TIM layer on the surface of the chip is joined to the coated surface of the heat removal device through a fluxless process. The method includes heating the joined carrier fixtures in a reflow oven."
The patent application was filed on Dec. 17, 2010 (12/971,737). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,205&OS=8,368,205&RS=8,368,205
Written by Arpi Sharma; edited by Anand Kumar.
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Oracle International Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Oracle International, Redwood City, Calif., has been assigned a patent (8,368,226) developed by Aparna Ramachandran, Cupertino, Calif., and Gary John Formica, San Jose, Calif., for a die power structure.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A die including a first set of power tiles arranged in a first array and having a first voltage; a second set of power tiles arranged in a second array offset from the first array and having a second voltage; a set of power mesh segments enclosed by the second set of power tiles and having the first voltage; a first power rail passing underneath the set of power mesh segments and the first set of power tiles; and a set of vias operatively connecting the power rail with the set of power mesh segments and the first plurality of power tiles."
The patent application was filed on March 5, 2012 (13/412,513). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,226&OS=8,368,226&RS=8,368,226
Written by Arpi Sharma; edited by Anand Kumar.
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QUALCOMM Assigned Patent for Sacrificial Material to Facilitate Thin Die Attach
ALEXANDRIA, Va., Feb. 8 -- QUALCOMM, San Diego, has been assigned a patent (8,368,232) developed by Omar J. Bchir, San Diego, for a "sacrificial material to facilitate thin die attach."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A sacrificial material applied to a thin die prior to die attach provides stability to the thin die and inhibits warpage of the thin die as heat is applied to the die and substrate during die attach. The sacrificial material may be a material that sublimates at a temperature near the reflow temperature of interconnects on the thin die. A die attach process deposits the sacrificial material on the die, attaches the die to a substrate, and applies a first temperature to reflow the interconnects. At the first temperature, the sacrificial material maintains substantially the same thickness. A second temperature is applied to sublimate the sacrificial material leaving a clean surface for the later packaging processes. Examples of the sacrificial material include polypropylene carbonate and polyethylene carbonate."
The patent application was filed on March 25, 2010 (12/731,526). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,232&OS=8,368,232&RS=8,368,232
Written by Arpi Sharma; edited by Anand Kumar.
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Applied Materials Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Applied Materials, Santa Clara, Calif., has been assigned a patent (8,368,308) developed by Samer Banna, San Jose, Calif., and Valentin N. Todorow, Palo Alto, Calif., for an "inductively coupled plasma reactor having RF phase control and methods of use thereof."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the present invention generally provide an inductively coupled plasma (ICP) reactor having a substrate RF bias that is capable of control of the RF phase difference between the ICP source (a first RF source) and the substrate bias (a second RF source) for plasma processing reactors used in the semiconductor industry. Control of the RF phase difference provides a powerful knob for fine process tuning. For example, control of the RF phase difference may be used to control one or more of average etch rate, etch rate uniformity, etch rate skew, critical dimension (CD) uniformity, and CD skew, CD range, self DC bias control, and chamber matching."
The patent application was filed on March 4, 2010 (12/717,358). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,308&OS=8,368,308&RS=8,368,308
Written by Arpi Sharma; edited by Anand Kumar.
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Swift Distribution Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Swift Distribution, Torrance, Calif., has been assigned a patent (8,367,919) developed by Michael Belitz, Manhattan Beach, Calif., Robin R. Slaton, Fort Collins, Colo., and Allen Killebrew, Longmont, Colo., for a musical support apparatus.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the inventive technology relate generally to item support apparatus. Although a focus of the inventive technology may, in some embodiments, be on support of musical related items such as musical instruments, keyboards, and sound speakers, the scope of the inventive technology and its applicability is not necessarily limited as such. In various embodiments, certain inventive technology provides enhanced functionality (e.g., stand adjustability), robust and simplified design (e.g., as may be found in a retention augmented item stand), enhanced performance (as may be found in a telescoping tube lock apparatus), and an ability to more easily control the elevation and lowering of heavy, stand supported items such as speakers."
The patent application was filed on Jan. 15, 2009 (12/863,168). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,367,919&OS=8,367,919&RS=8,367,919
Written by Arpi Sharma; edited by Anand Kumar.
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Apple Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Apple, Cupertino, Calif., has been assigned a patent (8,368,355) developed by Ching Yu John Tam, Los Gatos, Calif., for a "portable electronic device power manager with current limit feedback control loop modification for stabilizing an external power supply."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A portable electronic device has a battery to provide power to operate the device, a connector including a power supply pin to be coupled to an external power supply, and a power manager having a battery charger circuit that draws power through the power supply pin to charge the battery. The power manager has a current limit feedback control loop that limits the drawn current in accordance with a predetermined output current rating of the external power supply. The power manager automatically changes the behavior of its control loop to stabilize operation of the coupled external power supply. Other embodiments are also described and claimed."
The patent application was filed on April 14, 2010 (12/759,963). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,355&OS=8,368,355&RS=8,368,355
Written by Arpi Sharma; edited by Anand Kumar.
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MoSys Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- MoSys, Santa Clara, Calif., has been assigned a patent (8,368,217) developed by Michael J. Miller, Saratoga, Calif., Mark William Baumann, Campbell, Calif., and Richard S. Roy, Dublin, Calif., for an "integrated circuit package with segregated Tx and Rx data channels."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A chip layout isolates Rx terminals and Rx ports from Tx terminals and Tx ports. Tx terminals are grouped contiguously to each other, and are segregated as a group to a given edge of the package, Rx terminals are similarly grouped and segregated to a different edge of the package. Tx and Rx data channels are disposed in a respective single layer of the package, or both are disposed in a same single layer of the package. Rx ports and Tx ports are located at an approximate center of the package, with Tx and Rx ports disposed on respective opposite sides of an axis bisecting the package. Data signals received by, and transmitted from, the chip flow in a same direction, from a first edge of the package to the center of the package and from the center of the package to a second edge of the package, respectively."
The patent application was filed on July 3, 2012 (13/541,658). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,217&OS=8,368,217&RS=8,368,217
Written by Arpi Sharma; edited by Anand Kumar.
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Raytheon Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Raytheon, Waltham, Mass., has been assigned a patent (8,368,208) developed by Scott T. Johnson, Torrance, Calif., and Shadi S. Merhi, Cypress, Calif., for a semiconductor cooling apparatus.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "In some embodiments, a semiconductor cooling apparatus includes a monolithic array of cooling elements. Each cooling element of the monolithic array of cooling elements is configured to thermally couple to a respective semiconductor element of an array of semiconductor elements. At least two of the semiconductor elements have a different height and each cooling element independently flexes to conform to the height of the respective semiconductor element."
The patent application was filed on Oct. 1, 2010 (12/896,054). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,208&OS=8,368,208&RS=8,368,208
Written by Arpi Sharma; edited by Anand Kumar.
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Green Plug Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Green Plug, San Ramon, Calif., has been assigned a patent (8,368,252) developed by Gus Charles Pabon, Cupertino, Calif., for a "high- and low-power power supply with standby power saving features."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A power supply for providing power to an electrical device is described. The power supply converts a received input signal to a first electrical having a first voltage level at a first power converter. The power supply additionally converts the first electrical signal to a second electrical signal having a second voltage level at a second power converter, to provide the second electrical signal having the second voltage level to an output port. The power supply includes a circuit to selectively bypass the second power converter and provide the first electrical signal having the first voltage level from the first power converter to the output port. The first power converter may include one or more switches that may be disabled to disconnect power from the first power converter for additional standby power saving features."
The patent application was filed on Sept. 17, 2010 (12/885,156). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,252&OS=8,368,252&RS=8,368,252
Written by Arpi Sharma; edited by Anand Kumar.
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SpringLeaf Therapeutics Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- SpringLeaf Therapeutics, Boston, has been assigned a patent (8,368,285) developed by four co-inventors for an electrochemical actuators. The co-inventors are Yet-Ming Chiang, Framingham, Mass., Timothy E. Chin, San Jose, Calif., Michael J. Cima, Winchester, Mass., and J. Richard Gyory, Sudbury, Mass.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Devices and methods for providing electrochemical actuation are described herein. In one embodiment, an actuator device includes an electrochemical cell including a negative electrode and a positive electrode At least a portion of the negative electrode is formed with a material formulated to at least one of intercalate, de-intercalate, alloy with, oxidize, reduce, or plate with a first portion of the positive electrode to an extent different than with a second portion of the positive electrode such that a differential strain is imparted between the first portion and the second portion of the positive electrode and such that at least a portion of the electrochemical cell is displaced. The electrochemical cell includes a portion that is pre-bent along an axis of the electrochemical cell to define a fold axis and the displacement of the at least a portion of the electrochemical cell is maximized along the fold axis."
The patent application was filed on Dec. 16, 2011 (13/328,504). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,285&OS=8,368,285&RS=8,368,285
Written by Arpi Sharma; edited by Anand Kumar.
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Aerospace Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Aerospace, El Segundo, Calif., has been assigned a patent (8,368,155) developed by Margaret H. Abraham, Portola Valley, Calif., and David P. Taylor, Hawthorne, Calif., for "systems and methods for preparing freestanding films using laser-assisted chemical etch, and freestanding films formed using same."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems and methods for preparing freestanding films using laser-assisted chemical etch (LACE), and freestanding films formed using same, are provided. In accordance with one aspect a substrate has a surface and a portion defining an isotropically defined cavity; and a substantially continuous film is disposed at the substrate surface and spans the isotropically defined cavity. In accordance with another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a film is disposed at the substrate surface and spans the isotropically defined cavity, the film including at least one of hafnium oxide (HfO.sub.2), diamond-like carbon, graphene, and silicon carbide (SiC) of a predetermined phase. In accordance with still another aspect, a substrate has a surface and a portion defining an isotropically defined cavity; and a multi-layer film is disposed at the substrate surface and spans the isotropically defined cavity."
The patent application was filed on Aug. 26, 2010 (12/869,597). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,155&OS=8,368,155&RS=8,368,155
Written by Arpi Sharma; edited by Anand Kumar.
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California Institute of Technology Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- California Institute of Technology, Pasadena, Calif., has been assigned a patent (8,368,051) developed by four co-inventors for a "complementary barrier infrared detector (CBIRD)." The co-inventors are David Z. Ting, Arcadia, Calif., Sumith V. Bandara, Burke, Va., Cory J. Hill, Pasadena, Calif., and Sarath D. Gunapala, Stevenson Ranch, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An infrared detector having a hole barrier region adjacent to one side of an absorber region, an electron barrier region adjacent to the other side of the absorber region, and a semiconductor adjacent to the electron barrier."
The patent application was filed on July 10, 2009 (12/501,167). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,051&OS=8,368,051&RS=8,368,051
Written by Arpi Sharma; edited by Anand Kumar.
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Vishay-Siliconix Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Vishay-Siliconix, Santa Clara, Calif., has been assigned a patent (8,368,126) developed by seven co-inventors for a "trench metal oxide semiconductor with recessed trench material and remote contacts." The co-inventors are Deva N. Pattanayak, Saratoga, Calif., Kyle Terrill, Santa Clara, Calif., Sharon Shi, San Jose, Calif., Misha Lee, San Jose, Calif., Yuming Bai, Union City, Calif., Kam Lui, Santa Clara, Calif., and Kuo-In Chen, Los Altos, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Remote contacts to the polysilicon regions of a trench metal oxide semiconductor (MOS) barrier Schottky (TMBS) device, as well as to the polysilicon regions of a MOS field effect transistor (MOSFET) section and of a TMBS section in a monolithically integrated TMBS and MOSFET (SKYFET) device, are employed. The polysilicon is recessed relative to adjacent mesas. Contact of the source metal to the polysilicon regions of the TMBS section is made through an extension of the polysilicon to outside the active region of the TMBS section. This change in the device architecture relieves the need to remove all of the oxides from both the polysilicon and silicon mesa regions of the TMBS section prior to the contact step. As a consequence, encroachment of contact metal into the sidewalls of the trenches in a TMBS device, or in a SKYFET device, is avoided."
The patent application was filed on April 7, 2008 (12/098,950). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,126&OS=8,368,126&RS=8,368,126
Written by Arpi Sharma; edited by Anand Kumar.
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International Rectifier Assigned Patent for Hybrid Semiconductor Device having a GaN Transistor and a Silicon MOSFET
ALEXANDRIA, Va., Feb. 8 -- International Rectifier, El Segundo, Calif., has been assigned a patent (8,368,120) developed by Alexander Lidow, Hermosa Beach, Calif., Daniel M. Kinzer, El Segundo, Calif., and Srikant Sridevan, Redondo Beach, Calif., for a "hybrid semiconductor device having a GaN transistor and a silicon MOSFET."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A hybrid device including a silicon based MOSFET operatively connected with a GaN based device."
The patent application was filed on Sept. 2, 2011 (13/224,881). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,120&OS=8,368,120&RS=8,368,120
Written by Arpi Sharma; edited by Anand Kumar.
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Cymer Assigned Patent for EUV Light Source Glint Reduction System
ALEXANDRIA, Va., Feb. 8 -- Cymer, San Diego, has been assigned a patent (8,368,039) developed by Abhiram Govindaraju, San Diego, and William N. Partlo, Poway, Calif., for an "EUV light source glint reduction system."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An apparatus includes a light source having a gain medium for producing an amplified light beam of a source wavelength along a beam path to irradiate a target material in a chamber and to generate extreme ultraviolet light; and a subsystem overlying at least a portion of an internal surface of the chamber and configured to reduce a flow of light at the source wavelength from the internal surface back along the beam path."
The patent application was filed on April 5, 2010 (12/753,938). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,039&OS=8,368,039&RS=8,368,039
Written by Arpi Sharma; edited by Anand Kumar.
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HRL Laboratories Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- HRL Laboratories, Malibu, Calif., has been assigned a patent (8,368,119) developed by six co-inventors for an "integrated structure with transistors and schottky diodes and process for fabricating the same." The co-inventors are Louis Luh, Sunnyvale, Calif., Keh-Chung Wang, Thousand Oaks, Calif., Wah S. Wong, Montebello, Calif., Miroslav Micovic, Thousand Oaks, Calif., David Chow, Newbury Park, Calif., and Don Hitko, Grover Beach, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A process for fabricating an integrated group III nitride structure comprising high electron mobility transistors (HEMTs) and Schottky diodes, and the resulting structure, are disclosed. Integration of vertical junction Schottky diodes is enabled, and the parasitic capacitance and resistance as well as the physical size of the diode are minimized. A process for fabricating an integrated group III nitride structure comprising double-heterostructure field effect transistors (DHFETs) and Schottky diodes and the resulting structure are also disclosed."
The patent application was filed on May 19, 2011 (13/111,771). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,119&OS=8,368,119&RS=8,368,119
Written by Arpi Sharma; edited by Anand Kumar.
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Cree Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Cree, Durham, N.C., has been assigned a patent (8,368,100) developed by Matthew Donofrio, Raleigh, N.C., James Ibbetson, Santa Barbara, Calif., and Zhimin Jamie Yao, Goleta, Calif., for a "semiconductor light emitting diodes having reflective structures and methods of fabricating same."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Light emitting diodes include a diode region having first and second opposing faces that include therein an n-type layer and a p-type layer, an anode contact that ohmically contacts the p-type layer and extends on the first face, and a cathode contact that ohmically contacts the n-type layer and also extends on the first face. The anode contact and/or the cathode contact may further provide a hybrid reflective structure on the first face that is configured to reflect substantially all light that emerges from the first face back into the first face. Related fabrication methods are also described."
The patent application was filed on May 11, 2009 (12/463,709). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,100&OS=8,368,100&RS=8,368,100
Written by Arpi Sharma; edited by Anand Kumar.
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QUALCOMM MEMS Technologies Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- QUALCOMM MEMS Technologies, San Diego, has been assigned a patent (8,368,124) developed by four co-inventors for an "electromechanical devices having etch barrier layers." The co-inventors are Mark W. Miles, Atlanta, John Batey, Cupertino, Calif., Clarence Chui, San Jose, Calif., and Manish Kothari, Cupertino, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one embodiment, the invention provides a method for fabricating a microelectromechanical systems device. The method comprises fabricating a first layer comprising a film having a characteristic electromechanical response, and a characteristic optical response, wherein the characteristic optical response is desirable and the characteristic electromechanical response is undesirable; and modifying the characteristic electromechanical response of the first layer by at least reducing charge build up thereon during activation of the micro electromechanical systems device."
The patent application was filed on June 22, 2009 (12/489,250). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,124&OS=8,368,124&RS=8,368,124
Written by Arpi Sharma; edited by Anand Kumar.
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Hewlett-Packard Development Assigned Patent for Plasmon Enhanced Light-emitting Diodes
ALEXANDRIA, Va., Feb. 8 -- Hewlett-Packard Development, Houston, has been assigned a patent (8,368,050) developed by David A. Fattal, Mountain View, Calif., and Michael Renne Ty Tan, Menlo Park, Calif., for a "plasmon enhanced light-emitting diodes."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments of the present invention are directed to light-emitting diodes. In one embodiment of the present invention, a light-emitting diode comprises at least one quantum well sandwiched between a first intrinsic semiconductor layer and a second semiconductor layer. An n-type heterostructure is disposed on a surface of the first intrinsic semiconductor layer, and a p-type heterostructure is disposed on a surface of the second intrinsic semiconductor layer opposite the n-type semiconductor heterostructure. The diode also includes a metal structure disposed on a surface of the light-emitting diode. Surface plasmon polaritons formed along the interface between the metal-structure and the light-emitting diode surface extend into the at least one quantum well increasing the spontaneous emission rate of the transverse magnetic field component of electromagnetic radiation emitted from the at least one quantum well. In certain embodiments, the electromagnetic radiation can be modulated at a rate of about 10 Gb/s or faster."
The patent application was filed on Jan. 30, 2008 (12/864,210). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,050&OS=8,368,050&RS=8,368,050
Written by Arpi Sharma; edited by Anand Kumar.
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University of California, Japan Science and Technology Agency Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- The University of California, Oakland, Calif., and Japan Science and Technology Agency, Saitama Prefecture, Japan, have been assigned a patent (8,368,179) developed by nine co-inventors for a "miscut semipolar optoelectronic device." The co-inventors are John F. Kaeding, Mountain View, Calif., Dong-Seon Lee, Anyang-Si, South Korea, Michael Iza, Santa Barbara, Calif., Troy J. Baker, Raleigh, N.C., Hitoshi Sato, Kanagawa, Japan, Benjamin A. Haskell, Santa Barbara, Calif., James S. Speck, Goleta, Calif., Steven P. DenBaars, Goleta, Calif., and Shuji Nakamura, Santa Barbara, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for improved growth of a semipolar (Al,In,Ga,B)N semiconductor thin film using an intentionally miscut substrate. Specifically, the method comprises intentionally miscutting a substrate, loading a substrate into a reactor, heating the substrate under a flow of nitrogen and/or hydrogen and/or ammonia, depositing an In.sub.xGa.sub.1-xN nucleation layer on the heated substrate, depositing a semipolar nitride semiconductor thin film on the In.sub.xGa.sub.1-xN nucleation layer, and cooling the substrate under a nitrogen overpressure."
The patent application was filed on Dec. 6, 2011 (13/311,986). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,179&OS=8,368,179&RS=8,368,179
Written by Arpi Sharma; edited by Anand Kumar.
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University of California Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- The University of California, Oakland, Calif., has been assigned a patent (8,368,154) developed by four co-inventors for a "three dimensional folded MEMS technology for multi-axis sensor systems." The co-inventors are Alexander Trusov, Irvine, Calif., Montgomery C. Rivers, Irvine, Calif., Sergei A. Zotov, Irvine, Calif., and Andrei M. Shkel, McLean, Va.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An apparatus is fabricated with a plurality of semiconductor-device substrates and/or MEMS substrates with micromachined sensors, circuits, transducers, and/or MEMS devices fabricated on the plurality of substrates. A plurality of flexible hinges couple the plurality of substrates into a substantially flat two dimensional foldable assembly. Electrical interconnects coupled to the sensors, circuits, transducers, and/or MEMS devices extend other ones of the plurality of substrates. The foldable assembly of substrates is assembled or folded into a three dimensional polyhedral structure with the plurality of substrates configured in three dimensions to form defined relative orientations in space with respect to each other. The invention includes a wafer scale method of fabricating the apparatus."
The patent application was filed on Feb. 9, 2011 (13/024,112). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,154&OS=8,368,154&RS=8,368,154
Written by Arpi Sharma; edited by Anand Kumar.
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Altera Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Altera, San Jose, Calif., has been assigned a patent (8,368,174) developed by Xiaohong Jiang, San Jose, Calif., and Hong Shi, Fremont, Calif., for "compensation network using an on-die compensation inductor."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An integrated circuit with an on-die compensation network is presented. The compensation network includes a compensation inductor that has one terminal coupled to a bump pad of the die. Another terminal of the inductor is connected to a metal layer underneath the compensation inductor, forming a pi-configuration with the bump pad. The metal layer routes input and output signals from the integrated circuit. The invention can be used in either flip chip or wire bond applications."
The patent application was filed on July 9, 2010 (12/833,888). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,174&OS=8,368,174&RS=8,368,174
Written by Arpi Sharma; edited by Anand Kumar.
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Hewlett-Packard Development Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Hewlett-Packard Development, Houston, has been assigned a patent (8,368,118) developed by Shih-Yuan Wang, Palo Alto, Calif., Lars Helge Thylen, Huddinge, Sweden, and Sagi Varghese Mathai, Berkeley, Calif., for a "semiconductor structure having an ELOG on a thermally and electrically conductive mask."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A semiconductor structure includes a substrate, a thermally and electrically conductive mask positioned upon the substrate, and an epitaxial lateral over growth (ELOG) material positioned upon the thermally and electrically conductive mask."
The patent application was filed on Dec. 16, 2008 (13/133,370). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,118&OS=8,368,118&RS=8,368,118
Written by Arpi Sharma; edited by Anand Kumar.
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U.S. Navy Assigned Patent for Dipole Moment Term for an Electrically Small Antenna
ALEXANDRIA, Va., Feb. 8 -- The U.S. Navy has been assigned a patent (8,368,156) developed by Thomas O. Jones III, San Diego, for a "dipole moment term for an electrically small antenna."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention relates to a method for designing an electrically small antenna, in one embodiment, within an enclosing volume. In a preferred embodiment, the method comprises the steps of designing the electrically small antenna which has a general cross-sectional contour shape of an oblate spheroid from a top load portion to a stem portion below the top load portion. The oblate spheroid contour shape is represented by an antenna dipole moment algorithm which includes a dipole moment term. The method further comprises the steps of controlling the amplitude of the dipole moment term, including adjusting the amplitude of the dipole moment term to independently change the oblate spheroid contour shape, resulting in a change to the electric field outside the enclosing volume and a change to the electric field inside the enclosing volume."
The patent application was filed on March 31, 2011 (13/076,488). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,156&OS=8,368,156&RS=8,368,156
Written by Arpi Sharma; edited by Anand Kumar.
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SanDisk Technologies Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- SanDisk Technologies, Plano, Texas, has been assigned a patent (8,368,137) developed by Nima Mokhlesi, Los Gatos, Calif., and Jun Wan, San Jose, Calif., for a "dual bit line metal layers for non-volatile memory."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Structures and techniques are disclosed for reducing bit line to bit line capacitance in a non-volatile storage system. The bit lines are formed at a 4fpitch in each of two separate metal layers, and arranged to alternate between each of the layers. In an alternative embodiment, shields are formed between each of the bit lines on each metal layer."
The patent application was filed on June 26, 2007 (11/768,468). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,137&OS=8,368,137&RS=8,368,137
Written by Arpi Sharma; edited by Anand Kumar.
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International Rectifier Assigned Patent for III-nitride Materials Including Low Dislocation Densities and Methods Associated with the Same
ALEXANDRIA, Va., Feb. 8 -- International Rectifier, El Segundo, Calif., has been assigned a patent (8,368,117) developed by Edwin L. Piner, Cary, N.C., John C. Roberts, Hillsborough, N.C., and Pradeep Rajagopal, Raleigh, N.C., for "III-nitride materials including low dislocation densities and methods associated with the same."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Semiconductor structures including one, or more, III-nitride material regions (e.g., gallium nitride material region) and methods associated with such structures are provided. The III-nitride material region(s) advantageously have a low dislocation density and, in particular, a low screw dislocation density. In some embodiments, the presence of screw dislocations in the III-nitride material region(s) may be essentially eliminated. The presence of a strain-absorbing layer underlying the III-nitride material region(s) and/or processing conditions can contribute to achieving the low screw dislocation densities. In some embodiments, the III-nitride material region(s) having low dislocation densities include a gallium nitride material region which functions as the active region of the device. The low screw dislocation densities of the active device region (e.g., gallium nitride material region) can lead to improved properties (e.g., electrical and optical) by increasing electron transport, limiting non-radiative recombination, and increasing compositional/growth uniformity, amongst other effects."
The patent application was filed on March 29, 2010 (12/748,778). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,117&OS=8,368,117&RS=8,368,117
Written by Arpi Sharma; edited by Anand Kumar.
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University of California Assigned Patent for Light Emitting Diodes with a P-type Surface Bonded to a Transparent Submount to Increase Light Extraction Efficiency
ALEXANDRIA, Va., Feb. 8 -- The University of California, Oakland, Calif., has been assigned a patent (8,368,109) developed by six co-inventors for a "light emitting diodes with a p-type surface bonded to a transparent submount to increase light extraction efficiency." The co-inventors are Kenji Iso, Kanagawa, Japan, Hirokuni Asamizu, Goleta, Calif., Makoto Saito, Ibaraki, Japan, Hitoshi Sato, Kanagawa, Japan, Steven P. DenBaars, Goleta, Calif., and Shuji Nakamura, Santa Barbara, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An (Al,Ga,In)N-based light emitting diode (LED), comprising a p-type surface of the LED bonded with a transparent submount material to increase light extraction at the p-type surface, wherein the LED is a substrateless membrane."
The patent application was filed on Nov. 15, 2011 (13/296,611). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,109&OS=8,368,109&RS=8,368,109
Written by Arpi Sharma; edited by Anand Kumar.
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Gamma Medica-Ideas Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Gamma Medica-Ideas, Northridge, Calif., has been assigned a patent (8,368,029) developed by Douglas J. Wagenaar, Westlake Village, Calif., and Bradley E. Patt, Sherman Oaks, Calif., for "methods and systems of combining magnetic resonance and nuclear imaging."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A multi-modality imaging system for imaging of an object under study, e.g., a whole body or parts of the body of animals such as humans, other primates, swine, dogs, or rodents, that includes a magnetic resonance imaging apparatus and a cadmium zinc telluride (CZT)-family semiconductor, single-photon imaging apparatus within a magnetic field produced by the magnetic resonance imaging apparatus such that sequential or simultaneous imaging can be done with the two modalities using the same support bed of the object under study in the same, uninterrupted imaging session."
The patent application was filed on Oct. 11, 2011 (13/317,219). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,029&OS=8,368,029&RS=8,368,029
Written by Arpi Sharma; edited by Anand Kumar.
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International Business Machines Assigned Patent for Strained Thin Body Semiconductor-on-insulator Substrate and Device
ALEXANDRIA, Va., Feb. 8 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,368,143) developed by five co-inventors for a "strained thin body semiconductor-on-insulator substrate and device." The co-inventors are Stephen W. Bedell, Wappingers Falls, N.Y., Kangguo Cheng, Guilderland, N.Y., Bruce B. Doris, Albany, N.Y., Ali Khakifirooz, Mountain View, Calif., and Pranita Kulkarni, Slingerlands, N.Y.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of forming a strained, semiconductor-on-insulator substrate includes forming a second semiconductor layer on a first semiconductor substrate. The second semiconductor is lattice matched to the first semiconductor substrate such that the second semiconductor layer is subjected to a first directional stress. An active device semiconductor layer is formed over the second semiconductor layer such that the active device semiconductor layer is initially in a relaxed state. One or more trench isolation structures are formed through the active device layer and through the second semiconductor layer so as to relax the second semiconductor layer below the active device layer and impart a second directional stress on the active device layer opposite the first directional stress."
The patent application was filed on Nov. 21, 2011 (13/301,360). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,143&OS=8,368,143&RS=8,368,143
Written by Arpi Sharma; edited by Anand Kumar.
***
Cymer Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Cymer, San Diego, has been assigned a patent (8,368,041) developed by Matthew R. Graham, San Diego, Olav Haugan, San Diego, and William N. Partlo, San Diego, for a "system and method for compensating for thermal effects in an EUV light source."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and apparatus for compensating for thermal effects on the focal spot of a lens used to focus a laser beam on a target material at an irradiation site in a laser produced plasma (LPP) extreme ultraviolet (EUV) light system is disclosed. The EUV energy output of the light system is measured at sample intervals as a proxy for the laser power. The thermal load on the focusing lens is estimated from the measured EUV power, the expected change in the focal length of the lens for the thermal load is calculated, and the lens position is adjusted to compensate for the calculated focal length change. The actual position of the lens may be determined and compared to its desired position, and adjusted to insure that it remains in the desired position."
The patent application was filed on March 31, 2011 (13/077,958). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,041&OS=8,368,041&RS=8,368,041
Written by Arpi Sharma; edited by Anand Kumar.
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Micron Technology Assigned Patent for Reduced Signal Interface Memory Device, System, and Method
ALEXANDRIA, Va., Feb. 8 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,369,171) developed by Poorna Kale, Folsom, Calif., for a "reduced signal interface memory device, system, and method."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A memory has a serial interface. The serial interface is programmable to either use separate dedicated input and output pads, or to use one bidirectional pad. When one bidirectional pad is used, the interface signal count is reduced by one."
The patent application was filed on April 29, 2011 (13/097,568). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,369,171&OS=8,369,171&RS=8,369,171
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Skorpios Technologies Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Skorpios Technologies, Albuquerque, N.M., has been assigned a patent (8,368,995) developed by John Dallesasse, Geneva, Ill., Stephen B. Krasulick, Albuquerque, N.M., and William Kozlovsky, Sunnyvale, Calif., for a "method and system for hybrid integration of an opto-electronic integrated circuit."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An opto-electronic integrated circuit (OEIC) includes an SOI substrate, a set of composite optical transmitters, a set of composite optical receivers, and control electronics disposed in the substrate and electrically coupled to the set of composite optical transmitters and receivers. Each of the composite optical transmitters includes a gain medium including a compound semiconductor material and an optical modulator. Each of the composite optical receivers includes a waveguide disposed in the SOI substrate, an optical detector bonded to the SOI substrate, and a bonding region disposed between the SOI substrate and the optical detector. The bonding region includes a metal-assisted bond at a first portion of the bonding region and a direct semiconductor-semiconductor bond at a second portion of the bonding region. The OEIC also includes control electronics disposed in the SOI substrate and electrically coupled to the set of composite optical transmitters and the set of composite optical receivers."
The patent application was filed on March 30, 2011 (13/076,205). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,368,995&OS=8,368,995&RS=8,368,995
Written by Satyaban Rath; edited by Hemanta Panigrahi.
***
Greenliant Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- Greenliant, Santa Clara, Calif., has been assigned a patent (8,369,115) developed by Fredrik Buch, Santa Clara, Calif., and Michael S. Briner, San Jose, Calif., for a "time domain voltage step down capacitor based circuit."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A time domain voltage step down capacitor based circuit has an oscillating circuit for generating a clock signal. The circuit also has a capacitor based charge pump circuit for receiving the clock signal and an input voltage signal having an input current and generates an output voltage signal, less than the input voltage signal and an output current greater than the input current. The circuit further comprises a comparator circuit for receiving the output voltage signal, as a first input signal thereto, and a reference voltage signal as a second input signal thereto and compares the first input signal to the second input signal and generates a control signal in response thereto. Finally the control signal is supplied to the oscillating circuit to control the generating of the clock signal."
The patent application was filed on June 16, 2009 (12/485,735). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,369,115&OS=8,369,115&RS=8,369,115
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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General Motors Assigned Patent
ALEXANDRIA, Va., Feb. 8 -- General Motors, Detroit, has been assigned a patent (8,369,210) developed by Yao Hui Lei, Windsor, Calif., and Ki Hak Yi, Windsor, Calif., for a "retry for telematics packet data connection failures in CDMA 1xRTT network."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A technique and system are provided for executing retry procedures to resolve a packet connection failure during a CDMA 1xRTT packet session. In particular, the DTE is configured and controlled to retry based on either failure signals from the NAD or the Application Service Timer. Moreover, in one aspect, the DIE is configured and controlled to retry the packet connection selectively for traffic channel assignment failure, PPP connection failure, TCP/I
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