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TMCNet:  Precise Time Synchronization Technology for Distributed Automated Test System [Sensors & Transducers (Canada)]

[December 31, 2012]

Precise Time Synchronization Technology for Distributed Automated Test System [Sensors & Transducers (Canada)]

(Sensors & Transducers (Canada) Via Acquire Media NewsEdge) Abstract: Clock synchronization is essential to the distributed automated test system which is widely used in the world. A time stamp generation circuit based on FPGA is introduced, and a synchronization algorithm based on prediction is used to adjust the frequency of slave clocks in the system. The peer-to-peer communication and the seven-point communication test environments are built, and clock synchronization can achieve the precision of us. Copyright © 2012 IFSA.

Keywords: Distributed automated test, Precision time synchronization, Prediction.

(ProQuest: ... denotes formulae omitted.) 1. Introduction Automated test system is increasingly using distributed system technologies such as network communication, local computing, and distributed objects. Many of these applications will be enhanced by having an accurate system wide sense of time achieved by having local clocks in each sensor, actuator, or other system device. Ethernet based distributed automated test system (EBDATS) make it easy for multi-point test, otherwise, some test tasks must be completed under coordination work with several signals, and these signals such as high frequency signals' pulsecycle may even be up to lus. This requires EBDATS must have a precise synchronization mechanism to ensure the synchronization operation of the test units.

Network Time Protocol (NTP) is one of the most widely applied software clock synchronization method [1], but its 1 ms synchronous precision can't meet the requirements of the test tasks for EBDATS in many cases. IEEE 1588 Standard for Precision Clock Synchronization Protocol for Networked Measurement and Control Systems (PTP, Precision Time Protocol) [2] and the hardware trigger based synchronization method [3] can achieve the precision of ns, but they need specialized test equipment to support, and need to change the network link layer exchanging or routing equipments [4].

Some universal test equipments can provide high precise clock synchronization, but they can't meet the demand because of the particularity of signals in some special test tasks. In this case, the hardware with high precise clock synchronization function is needed to acquire and process special signals, and the corresponding precise clock synchronization method is needed. A time stamp (time with respect to an epoch) generation circuit based on FPGA is introduced in this paper, this method uses serial different input pulse but asynchronous message as the synchronous clock source. A clock drift correction algorithm based on prediction is provided, this algorithm ensured that the hardware can keep high precision synchronization with each other and need not to change the network link layer and the routing equipments.

2. Implementation 2.1. Time Stamp Offset Analysis 2.1.1. Time Stamp Additional Offset In Ethernet, message package is received by physical layer, then sent to MAC layer, MAC layer sends the package to the host memory packet, and at the same time it generates an interrupt to notice the host that there are some packets received. Host responses to the interrupt, sends the packet to upper protocol stack, finally the packet reach the application layer [5]. The whole process is shown in Fig. 1 .Timestamp can be generated in several positions: MAC (media access control) layer, drive layer as well as the application layer.

The time delay caused by cache and interrupt response is different when the position of generating time stamp is different. As a result, the time stamp value and the real time deviation of the packet is not the same [6], which has produced additional time stamp additional offset. The timing information captured at physical or MAC layer will have a higher accuracy.

Definition 1: time stamp additional offset. Set the real time of data packets for t, the physical delay of packets for Pt, interrupt response time for /,, driver delay for Dt, the application layer processing delays for Au then the time stamp adding time St : ... (1) Time stamp additional offset: ... (2) There are several time stamp additional offset sources, most of them have millisecond rimescale. Until now the attempts to improve the accuracy of the time stamp additional offset always face to the factors above: reference [7] improved the accuracy of time stamp by changing the time stamp position from the application layer to drive layer, finally increased the accuracy of the one-way network delay measurement and further; Reference [8] moved the time stamp position to physical link layer, and reduced the synchronous packets delay in the MAC through the priority queues.

2.1.2. Time Stamp Inherent Offset The clock used to produce time stamp is affected by the jitter and drift of oscillators, and its frequency is instability [9-10], different oscillators produce different clock drift [11].

Definition 2: Time stamp inherent offset: set the current real time for t, clock resolution for «, the clock drift coefficient for/ , the time stamp value of node i is ..., then the time stamp inherent offset: ... (3) The time stamp offset contains time stamp inherent offset and time stamp additional offset: ... (4) 2.2. Design and Implementation of Precise Time Stamp System 2.2.1. Time Stamp Representation Type Analysis In EBDATS, the accuracy of time stamp depends on the characteristics of the oscillator (drift) and the frequency of the synchronization procedure (determined by the software). To get a higher precision of the system clock, the hardware circuit must be introduced to insert time stamp at the bottom layer to reduce the influence of software; but the characteristics of the oscillator (drift) can not be eliminated thoroughly, so some corresponding algorithm must be introduced to compensate the error, and finally reduce its influence to the system.

Time stamp generating circuit is shown in Fig. 2, the core is the comprehensive frequency adjust module (ADJ), this circuit adjust generating frequency of the clock by changing the value of frequency controlling word. Set the input clock frequency of the ADJ module for fref, the clock frequency output for fsym frequency controlling word for Kadj (32 bit), then: ... (5) To get a snapshot of the time, the TimeRepresentation type is defined, this time is 64-bit format with the upper 32 bits providing time in seconds (time stamp high register in Fig. 2), and the lower 32 bits indicating time in nanoseconds (time stamp low register in Fig. 2) .

struct TimeRepresentation { UInteger32 seconds; Integer32 nanoseconds; }; Actually, the precision of the clock can be changed by setting the lower 32-m bit to 0 (m<32), in this way, we can get a 2"ms precision for the clock.

2.2.2. Clock Drift Correction Algorithm Based On Prediction The synchronization for seconds can be easily achieved by NTP protocol, only the lower 32 bit time stamp value is generated by the internal counter. The counter clock can be divided by a prescaler^", when the counter overflow event encountered, and the time stamp high register plus one. To ensure that the time between initialization to overflow of the counter is 1 second, then ... (6) In many applications of EBDATS, the local time of nodes is not required to be synchronization with UTC, but may be required to keep synchronism with a master clock in the system to enter a specified precision. Two clocks are synchronized to a specified uncertainty if they have the same epoch, and measurements of any time interval by both clocks differ by no more than the specified uncertainty.

In the synchronous process, master clock connected to slave clocks by different serial bus. The master clock outputs a PPS pulse every 1 s, the pulse is 125 ns wide. The slave clocks interrupt when they receive the pulse from master clock, and read time stamp value form the time stamp register, then use the synchronous algorithm based on prediction to adjust the frequency controlling word Kadj. The slave clock frequency drift with respect to the master clock is corrected over a period of time, and finally reach a minimum deviation from master clock. The longer correction time helps maintain linear time and does not introduce drastic changes (or a large jitter) in the reference time between Sync pulse intervals.

The synchronous algorithm based on prediction can be divided into two stages in the implementation process: starting stage (Fig. 3) and synchronization stage. Starting Stage Step 1 : The slave clock begins to work, it needs to be initialized, and this time is set for Ato, To is the moment when the node complete the initialization. When the next time the sync pulse from master clock arrives, the slave clock reads and records the time stamp Ti.

Step 2: Read the time stamp T2, At2 = T2 - Tu then the actual clock frequency: ... (7) In step 2, the frequency control word Kadf is also used, so we can suppose that the time difference will reach to 2 2 in step 3, calculating the frequency control word Kad/' ... (8) Step 3: Calculate the frequency control word Kadf with the current time stamp T3: ... (9) The slave time stamp is closer to the master time after step 3, but it is not the normal pursue stage, the offset is not useful, the frequency control word Kad} is calculated in synchronization stage. Synchronization Stage Every moment of receive the pulse from the master clock, the time stamp Ti is recorded, and the offset is calculated: Ah= Ti-T^.

The prediction value of the time offset for the forward two steps is calculated: ... (10) ... (11) The frequency control word Kl+1adj for next step is calculated through Kad/ of the current step: Kadjl+1 =[2m + e0 (1) + e1 (i)xKadji/?ti (12) 3. Performance Tests In order to verify the precision of the time stamp in the automatic system, the peer-to-peer communication and the multi-points communication test environments were built.

In each test environment, the slave clock keep synchronization with the master clock when the Is pulse comes. There are something need to be pay attention to: 1) To eliminate software delay effects, time stamp registers value is locked when the second pulse comes, the values used in the software are the locked value, this method can ensure that the value read from register can take away from the software delay; 2) Frequency control word Kadj doesn't take effect immediately after updated but until the next pulse comes, in this way, the final time stamp value can be prevented from being influenced by software written delay.

3.1. Peer-to-peer Communication A slave clock node is connected to the master clock with different serial bus and the two nodes can exchange their sync-message through the network. In this module, we can test the correctness of the synchronous algorithm, system is connected as shown in Fig. 4.

To achieve the clock precision of 50 ns, the value of m in formula (6) should be set as 25, the update clock frequency ^"should be 20 MHz. If the frequency of the oscillator^/ is 40 MHz, then we can initialize the frequency control word Kadf = 225/(40/20) = 0x1000000, the slave clock calculate the predicted value KadJ+l in every pulse period, and use the new frequency^ to keep synchronization with the master clock.

Allan variance [12] d (t) is used to indicate the time offset: ... (13) k = 1,2...M-1 In formula (13), ?i is the offset of the slave clock at the moment *,·, d (t) is the statistics information for frequency variance.

3.2. Multi-points Communication Network is constituted by 7 nodes, which contains one master clock and 6 slave clocks, we can get the relative accuracy synchronization by compare the PPS signals of the 7 nodes, the module is shown in Fig. 7.

Although the information is enchanged through switch, only NTP synchronization message is network related, and the delay caused by network is lower than 1 second. In the synchronization system, the accuracy of time stamp will not descend with the increase of the slave clock number, so the synchronization accuracy in multi-point communication system keep the same as in peer-to-peer communication system, but a longer correction time helps maintain linear time with master clock between Sync pulse intervals.

4. Conclusions The clock synchronization circuit and the clock drift correction algorithm based on prediction designed in this paper can support system-wide synchronization accuracy in the submicrosecond range, and the implementation of exchanging information is also based on the original Ethernet. In this way, the proper automatic test system, which needs a higher precision synchronization less than 1 ms can be designed without expensive universal equipments.

References [1]. Mills D., Thyagarajan ., Huffman B. C, Internet timekeeping around the globe, in Proceedings of the Precision Time and Time Interval (PTTI) Applications and Planning Meeting, New York, 1997, pp. 365-371.

[2]. IEEE Std. 1588-2002, IEEE Standard for a Precision Clock synchronization protocol for Networked Measurement and Control Systems, November 2002.

[3]. Baragona R., Battaglia F., Outlier detection in multivariate time series by Independent Component Analysis, Neural Computation, 19, 1, 2010, pp. 1962-1984.

[4]. Lu Yi, Marconi T, Gaydadjiev G, et al., An Efficient Algorithm for Free Resources Management on the FPGA, in Proceedings of the DATE '08, New York, USA, ACM Press, 2008.

[5]. Steiger C, Walder H., Platzner M., Operating Systems for Reconfigurable Embedded Platforms: Online Scheduling of Real-time Tasks, IEEE Transactions on Computers, 2009, 53, 11, pp. 1393-1407.

[6]. Gurewitz O., Cidon I., Sidi M., Network classes time protocol based on clock offset optimization, IEEE/ACM Trans on Networking, 14, 4, 2006, pp. 876-888.

[7]. Li Wenwei, Zhang Dafang, Xie Gaogang, et al., A high precision approach of network delay measurement based on general PC, Journal of Software, 17, 2, 2008, pp. 275-2,4.

[8]. Yamada Y., Ohta S., Uematsu H., Hardware-based precise time synchronization on Gb/s Ethernet enhanced with preemptive priority, IEICE TRANSACTIONS on Communications, Vol. E89-B, No.3, March 2006, pp.683-689.

[9]. Ren Fengyuan, Dong Siying, He Tao, et al., A time synchronization mechanism and algorithm based on phase lock loop, Journal of Software, 18, 2, 2007, pp. 372-38.

[10]. Sanchez D. Secure, Accurate and precise time synchronization for wireless sensor networks, in Proceedings of the 3rd ACM Workshop on QoS and Security for Wireless and Mobil Networks, New York, ACM, 2007, pp. 105-112.

[11]. Schmid T., Charbiwala Z., Friedman J., et al., Exploiting manufacturing variations for compensating environ ment-induced clock drift in time synchronization, in Proceedings of the 2008 ACM SIGMETRICS Int. Conf. on Measurement and Modeling, New York: ACM, 2008, pp. 97-108.

[12].P. Loschmidt, R. Exel, A. Nagy, G. Gaderer, Limits of Synchronization Accuracy Using Hardware Support in IEEE 1588, in Proceedings of the International Symposium for Precision Clock Synchronization for Measurement, Control and Communication (ISPCS' 2008), 22-26 September 2008, pp. 12- 16.

1 Yan XU, l Ming LI, and 2 Jiangtao DONG 1 Electronic and Optical Engineering Department, Ordnance Engineering College, Shijiazhuang, HeBei, 050003, China 2 The 54th Research Institute of China Electronics Technology Group Corporation, Shijiazhuang, HeBei, 050081, China Tel.:86-15930123160 E-mail: Received: 11 September 2012 /Accepted: 11 October 2012 /Published: 20 November 2012 (c) 2012 International Frequency Sensor Association

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