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U.S. Patents Awarded to Inventors in Vermont (May 5)
(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service
Targeted News Service
ALEXANDRIA, Va., May 5 -- The following federal patents were awarded to inventors in Vermont.
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International Business Machines Assigned Patent for BEOL Wiring Structures
ALEXANDRIA, Va., May 5 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,169,050) developed by Douglas M. Daley, Essex Junction, Vt., Mete Erturk, Alburg, Vt., and Edward J. Gordon, Bristol, Vt., for "BEOL wiring structures that include an on-chip inductor and an on-chip capacitor, and design structures for a radiofrequency integrated circuit."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Back-end-of-line (BEOL) wiring structures that include an on-chip inductor and an on-chip capacitor, as well as design structures for a radiofrequency integrated circuit. The on-chip inductor and an on-chip capacitor, which are fabricated as conductive features in different metallization levels, are vertically aligned with each other. The on-chip capacitor, which is located between the on-chip inductor and the substrate, may serve as a Faraday shield for the on-chip inductor. Optionally, the BEOL wiring structure may include an optional Faraday shield located vertically either between the on-chip capacitor and the on-chip inductor, or between the on-chip capacitor and the top surface of the substrate. The BEOL wiring structure may include at least one floating electrode capable of being selectively coupled with the electrodes of the on-chip capacitor to permit tuning, during circuit operation, of a resonance frequency of an LC resonator that further includes the on-chip inductor."
The patent application was filed on June 26, 2008 (12/146,555). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,169,050&OS=8,169,050&RS=8,169,050
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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International Business Machines Assigned Patent for Asymmetric Junction Field Effect Transistor
ALEXANDRIA, Va., May 5 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,169,007) developed by five co-inventors for an "asymmetric junction field effect transistor." The co-inventors are Frederick G. Anderson, South Burlington, Vt., David S. Collins, Williston, Vt., Richard A. Phelps, Colchester, Vt., Robert M. Rassel, Colchester, Vt., and Michael J. Zierak, Colchester, Vt.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch."
The patent application was filed on March 1, 2011 (13/037,485). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,169,007&OS=8,169,007&RS=8,169,007
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Micron Technology Assigned Patent
ALEXANDRIA, Va., May 5 -- Micron Technology, Boise, Idaho, has been assigned a patent (8,168,502) developed by Leonard Forbes, Corvallis, Ore., Kie Y. Ahn, Chappaqua, N.Y., and Arup Bhattacharyya, Essex Junction, Vt., for a "tantalum silicon oxynitride high-K dielectrics and metal gates."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Electronic apparatus and methods of forming the electronic apparatus include a tantalum silicon oxynitride film on a substrate for use in a variety of electronic systems. The tantalum silicon oxynitride film may be structured as one or more monolayers. The tantalum silicon oxynitride film may be formed using a monolayer or partial monolayer sequencing process. Metal electrodes may be disposed on a dielectric containing a tantalum silicon oxynitride film."
The patent application was filed on Aug. 12, 2010 (12/855,556). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8168502.PN.&OS=PN/8168502&RS=PN/8168502
Written by Kusum Sangma; edited by Anand Kumar.
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International Business Machines Assigned Patent for Double Gate Depletion Mode MOSFET
ALEXANDRIA, Va., May 5 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,168,500) developed by four co-inventors for a "double gate depletion mode MOSFET." The co-inventors are John B. Campi, Westford, Vt., Richard A. Phelps, Colchester, Vt., Robert M. Rassel, Colchester, Vt., and Michael J. Zierak, Essex Junction, Vt.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A metal-oxide-semiconductor field effect transistor (MOSFET) has a body layer that follows the contour of exposed surfaces of a semiconductor substrate and contains a bottom surface of a shallow trench and adjoined sidewalls. A bottom electrode layer vertically abuts the body layer and provides an electrical bias to the body layer. A top electrode and source and drain regions are formed on the body layer. The thickness of the body layer is selected to allow full depletion of the body layer by the top electrode and a bottom electrode layer. The portion of the body layer underneath the shallow trench extends the length of a channel to enable a high voltage operation. Further, the MOSFET provides a double gate configuration and a tight control of the channel to enable a complete pinch-off of the channel and a low off-current in a compact volume."
The patent application was filed on Jan. 25, 2011 (13/013,311). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8168500.PN.&OS=PN/8168500&RS=PN/8168500
Written by Kusum Sangma; edited by Anand Kumar.
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International Business Machines Assigned Patent for Self-dicing Chips Using Through Silicon Vias
ALEXANDRIA, Va., May 5 -- International Business Machines, Armonk, N.Y., has been assigned a patent (8,168,474) developed by seven co-inventors for a "self-dicing chips using through silicon vias." The co-inventors are James W. Adkisson, Jericho, Vt., Panglijen Candra, Williston City, Vt., Thomas J. Dunbar, Burlington, Vt., Jeffrey P. Gambino, Westford, Vt., Mark D. Jaffe, Shelburne, Vt., Robert K. Leidy, Burlington, Vt., and Yen L. Lim, Essex Junction, Vt.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems and methods simultaneously form first openings and second openings in a substrate. The first openings are formed smaller than the second openings. The method also simultaneously forms a first material in the first openings and the second openings. The first material fills the first openings, and the first material lines the second openings. The method forms a second material different than the first material in the second openings. The second material fills the second openings. The method forms a plurality of integrated circuit structures over the first material and the second material within the second openings. The method applies mechanical stress to the substrate to cause the substrate to split along the first openings."
The patent application was filed on Jan. 10, 2011 (12/987,402). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8168474.PN.&OS=PN/8168474&RS=PN/8168474
Written by Kusum Sangma; edited by Anand Kumar.
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