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U.S. Patents Awarded to Inventors in California (April 27)
(Targeted News Service Via Acquire Media NewsEdge) Targeted News Service
Targeted News Service
ALEXANDRIA, Va., April 27 -- The following federal patents were awarded to inventors in California.
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Ovonyx Assigned Patent
ALEXANDRIA, Va., April 27 -- Ovonyx, Troy, Mich., has been assigned a patent (8,164,949) developed by Semyon D. Savransky, Newark, Calif., for "reducing drift in chalcogenide devices."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Chalcogenide materials conventionally used in chalcogenide memory devices and ovonic threshold switches may exhibit a tendency called drift, wherein threshold voltage or resistance changes with time. By providing a compensating material which exhibits an opposing tendency, the drift may be compensated. The compensating material may be mixed into a chalcogenide, may be layered with chalcogenide, may be provided with a heater, or may be provided as part of an electrode in some embodiments. Both chalcogenide and non-chalcogenide compensating materials may be used."
The patent application was filed on March 25, 2011 (13/072,002). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,949.PN.&OS=PN/8,164,949&RS=PN/8,164,949
Written by Shabnam Sheikh; edited by Jaya Anand.
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Finisar Assigned Patent
ALEXANDRIA, Va., April 27 -- Finisar, Sunnyvale, Calif., has been assigned a patent (8,164,922) developed by Daehwan Daniel Kim, Sunnyvale, Calif., for a "heat management in an electronic module."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "In one example, a heat management system suitable for use in connection with an electronic module is disclosed. In a disclosed embodiment the heat management system includes a module guide configured to receive an electronic module. At least two heat sink elements are configured and arranged for movement independent of each other. At least two retention elements are configured to bias a respective heat sink element against any electronic module that is positioned within the module guide."
The patent application was filed on Sept. 27, 2010 (12/891,677). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,922.PN.&OS=PN/8,164,922&RS=PN/8,164,922
Written by Shabnam Sheikh; edited by Jaya Anand.
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Applied Materials Assigned Patent
ALEXANDRIA, Va., April 27 -- Applied Materials, Santa Clara, Calif., has been assigned a patent (8,163,626) developed by six co-inventors for an "enhancing NAND flash floating gate performance." The co-inventors are Johanes Swenburg, Los Gatos, Calif., David Chu, Campbell, Calif., Theresa Kramer Guarini, San Jose, Calif., Yonah Cho, Sunnyvale, Calif., Udayan Ganguly, San Jose, Calif., and Lucien Date, Ottignies-Louvain-La-Neuve, Belgium.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Embodiments described herein generally relate to flash memory devices and methods for manufacturing flash memory devices. In one embodiment, a method for selective removal of nitrogen from the nitrided areas of a substrate is provided. The method comprises positioning a substrate comprising a material layer disposed adjacent to an oxide containing layer in a processing chamber, exposing the substrate to a nitridation process to incorporate nitrogen onto the material layer and the exposed areas of the oxide containing layer, and exposing the nitrided material layer and the nitrided areas of the oxide containing layer to a gas mixture comprising a quantity of a hydrogen containing gas and a quantity of an oxygen containing gas to selectively remove nitrogen from the nitrided areas of the oxide containing layer relative to the nitrided material layer using a radical oxidation process."
The patent application was filed on June 15, 2010 (12/815,659). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,626.PN.&OS=PN/8,163,626&RS=PN/8,163,626
Written by Shabnam Sheikh; edited by Jaya Anand.
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Western Digital Assigned Patent for Read Head
ALEXANDRIA, Va., April 27 -- Western Digital, Fremont, Calif., has been assigned a patent (8,164,858) developed by Mark D. Moravec, Gilroy, Calif., Subrata I. Gusti Made, Bangkok, Thailand, and Santi Pumkrachang, Bangkok, Thailand, for a "read head having conductive filler in insulated hole through substrate."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A novel read head includes a substrate having a trailing face and a leading face opposite the trailing face. The substrate includes a first hole therethrough that extends continuously from the trailing face to the leading face. The read head also includes a read transducer disposed on the trailing face, and a first plurality of electrically conductive trailing connection pads disposed on the trailing face. A first insulative layer is disposed on an inner surface of the first hole. A first electrically conductive filler is disposed in the first hole but is insulated from the substrate by the first insulative layer. A first electrically conductive leading connection pad is disposed on the leading face and is electrically connected to the first conductive filler."
The patent application was filed on Nov. 4, 2009 (12/612,575). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,858.PN.&OS=PN/8,164,858&RS=PN/8,164,858
Written by Shabnam Sheikh; edited by Jaya Anand.
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SanDisk Assigned Patent
ALEXANDRIA, Va., April 27 -- SanDisk, Milpitas, Calif., has been assigned a patent (8,163,593) developed by Usha Raghuram, San Jose, Calif., and S. Brad Herner, San Jose, Calif., for a "method of making a nonvolatile phase change memory cell having a reduced contact area."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method is described to form a nonvolatile memory cell having a contact area between a phase-change material such as a chalcogenide and a heat source which is smaller than photolithographic limits. A conductive or semiconductor pillar is exposed at a dielectric surface and recessed by selective etch. A thin, conformal layer of a spacer material is deposited on the dielectric top surface, the pillar top surface, and the sidewalls of the recess, then removed from horizontal surfaces by anistropic etch, leaving a spacer on the sidewalls defining a reduced volume within the recess. The phase change material is deposited within the spacer, having a reduced contact area to the underlying conductive or semiconductor pillar."
The patent application was filed on Nov. 16, 2006 (11/560,792). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,593.PN.&OS=PN/8,163,593&RS=PN/8,163,593
Written by Shabnam Sheikh; edited by Jaya Anand.
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Western Digital Assigned Patent
ALEXANDRIA, Va., April 27 -- Western Digital, Fremont, Calif., has been assigned a patent (8,164,864) developed by Christian Kaiser, San Jose, Calif., Laurence L. Chen, Hayward, Calif., and Qunwen Leng, Palo Alto, Calif., for a "method and system for fabricating magnetic transducers with improved pinning."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and system for providing a magnetic transducer are disclosed. The method and system include providing a magnetic element that includes a free layer, a pinned layer, and a nonmagnetic spacer layer between the free layer and the pinned layer. The nonmagnetic spacer layer is a tunneling barrier layer. The free layer is configured to be biased in a first direction. The pinned layer has a pinned layer magnetization configured to be pinned in a second direction that is at a first angle from perpendicular to the ABS. The first angle is nonzero and different from ninety degrees. The second direction and the first direction form a second angle that is different from ninety degrees."
The patent application was filed on July 16, 2009 (12/504,030). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,864.PN.&OS=PN/8,164,864&RS=PN/8,164,864
Written by Shabnam Sheikh; edited by Jaya Anand.
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Alpha and Omega Semiconductor Assigned Patent
ALEXANDRIA, Va., April 27 -- Alpha and Omega Semiconductor, Sunnyvale, Calif., has been assigned a patent (8,163,618) developed by four co-inventors for a "power MOSFET device structure for high frequency applications." The co-inventors are Anup Bhalla, Santa Clara, Calif., Daniel Ng, Campbell, Calif., Tiesheng Li, San Jose, Calif., and Sik K. Lui, Sunnyvale, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "This invention discloses a new switching device supported on a semiconductor that includes a drain disposed on a first surface and a source region disposed near a second surface of said semiconductor opposite the first surface. The switching device further includes an insulated gate electrode disposed on top of the second surface for controlling a source to drain current. The switching device further includes a source electrode interposed into the insulated gate electrode for substantially preventing a coupling of an electrical field between the gate electrode and an epitaxial region underneath the insulated gate electrode. The source electrode further covers and extends over the insulated gate for covering an area on the second surface of the semiconductor to contact the source region. The semiconductor substrate further includes an epitaxial layer disposed above and having a different dopant concentration than the drain region. The insulated gate electrode further includes an insulation layer for insulating the gate electrode from the source electrode wherein the insulation layer having a thickness depending on a Vgsmax rating of the vertical power device."
The patent application was filed on Feb. 9, 2010 (12/658,450). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,618.PN.&OS=PN/8,163,618&RS=PN/8,163,618
Written by Shabnam Sheikh; edited by Jaya Anand.
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Qualcomm Mems Technologies Assigned Patent
ALEXANDRIA, Va., April 27 -- Qualcomm Mems Technologies, San Diego, has been assigned a patent (8,164,815) developed by five co-inventors for "MEMS cavity-coating layers and methods." The co-inventors are Ana R. Londergan, Santa Clara, Calif., Bangalore R. Natarajan, Cupertino, Calif., Evgeni Gousev, Saratoga, Calif., James Randolph Webster, San Jose, Calif., and David Heald, Solvang, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Devices, methods, and systems comprising a MEMS device, for example, an interferometric modulator, that comprises a cavity in which a layer coats multiple surfaces. The layer is conformal or non-conformal. In some embodiments, the layer is formed by atomic layer deposition (ALD). Preferably, the layer comprises a dielectric material. In some embodiments, the MEMS device also exhibits improved characteristics, such as improved electrical insulation between moving electrodes, reduced stiction, and/or improved mechanical properties."
The patent application was filed on June 7, 2010 (12/795,294). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,815.PN.&OS=PN/8,164,815&RS=PN/8,164,815
Written by Shabnam Sheikh; edited by Jaya Anand.
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Opto-Knowledge Systems Assigned Patent
ALEXANDRIA, Va., April 27 -- Opto-Knowledge Systems, Torrance, Calif., has been assigned a patent (8,164,813) developed by Nahum Gat, Manhattan Beach, Calif., and Jingyi Zhang, Torrance, Calif., for a "non-circular continuous variable aperture or shutter for infrared cameras."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A continuous variable non-circular aperture for an infra-red camera is formed by a plurality of positionable metal blades arranged to define there between an aperture of non-circular shape. A rotatable actuator plate positions the blades. Actuator rotation in one direction moves the metal blades to increase the size of the non-circular aperture without changing the non-circular shape of the aperture and vice-versa when the actuator plate is rotated in the opposite direction also maintaining the non-circular aperture shape. A preferred non-circular shape for a continuous variable aperture now possible is a rectangle; another is configured as a racetrack."
The patent application was filed on Dec. 31, 2007 (12/006,428). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,813.PN.&OS=PN/8,164,813&RS=PN/8,164,813
Written by Shabnam Sheikh; edited by Jaya Anand.
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Innovalight Assigned Patent
ALEXANDRIA, Va., April 27 -- Innovalight, Sunnyvale, Calif., has been assigned a patent (8,163,587) developed by four co-inventors for "methods of using a silicon nanoparticle fluid to control in situ a set of dopant diffusion profiles." The co-inventors are Giuseppe Scardera, Sunnyvale, Calif., Dmitry Poplavskyy, San Jose, Calif., Michael Burrows, Cupertino, Calif., and Sunil Shah, Union City, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of forming a multi-doped junction on a substrate is disclosed. The method includes providing the substrate doped with boron atoms, the substrate comprising a front substrate surface, and depositing an ink on the front substrate surface in an ink pattern, the ink comprising a set of nanoparticles and a set of solvents. The method further includes heating the substrate in a baking ambient to a first temperature of between about 200.degree. C. and about 800.degree. C. and for a first time period of between about 3 minutes and about 20 minutes in order to create a densified film ink pattern. The method also includes exposing the substrate to a dopant source in a diffusion furnace with a deposition ambient, the deposition ambient comprising POCl.sub.3, a carrier N.sub.2 gas, a main N.sub.2 gas, and a reactive O.sub.2 gas, wherein a ratio of the carrier N.sub.2 gas to the reactive O.sub.2 gas is between about 1:1 to about 1.5:1, at a second temperature of between about 700.degree. C. and about 1000.degree. C., and for a second time period of about 5 minutes to about 35 minutes. The method also includes heating the substrate in a drive-in ambient to a third temperature of between about 800.degree. C. and about 1100.degree. C."
The patent application was filed on July 21, 2009 (12/506,811). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,587.PN.&OS=PN/8,163,587&RS=PN/8,163,587
Written by Shabnam Sheikh; edited by Jaya Anand.
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National Semiconductor Assigned Patent
ALEXANDRIA, Va., April 27 -- National Semiconductor, Santa Clara, Calif., has been assigned a patent (8,163,619) developed by Jeng-Jiun Yang, Sunnyvale, Calif., Constantin Bulucea, Sunnyvale, Calif., and Sandeep R. Bahl, Palo Alto, Calif., for a "fabrication of semiconductor structure having asymmetric field-effect transistor with tailored pocket portion along source/drain zone."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An asymmetric insulated-gate field effect transistor (100U or 102U) is provided along an upper surface of a semiconductor body so as to have first and second source/drain zones (240 and 242 or 280 and 282) laterally separated by a channel zone (244 or 284) of the transistor's body material. A gate electrode (262 or 302) overlies a gate dielectric layer (260 or 300) above the channel zone. A pocket portion (250 or 290) of the body material more heavily doped than laterally adjacent material of the body material extends along largely only the first of the S/D zones and into the channel zone. The vertical dopant profile of the pocket portion is tailored to reach a plurality of local maxima at respective locations (PH-1-PH-3-NH-3) spaced apart from one another. This typically enables the transistor to have reduced current leakage."
The patent application was filed on March 27, 2009 (12/382,967). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,619.PN.&OS=PN/8,163,619&RS=PN/8,163,619
Written by Shabnam Sheikh; edited by Jaya Anand.
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Apple Assigned Patent
ALEXANDRIA, Va., April 27 -- Apple, Cupertino, Calif., has been assigned a patent (8,164,932) developed by Nicholas A. Sims, San Francisco, and Jeffrey Terlizzi, San Francisco, for a "power converter with automatic mode switching."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A power converter is provided that has an alternating-current (AC) to direct-current (DC) switched-mode power converter circuit that converts alternating-current power into direct-current power for powering an attached electronic device. Power can be conserved by automatically placing the power converter circuit in a low-power standby mode of operation whenever the electronic device is detached from the power converter. A monitoring circuit can be powered by a capacitor or other energy storage element while the power converter is operating in the standby mode. If the monitoring circuit detects an output voltage change that is indicative of attachment of the electronic device or if the storage element needs to be replenished, the monitoring circuit can place the power converter circuit in an active mode of operation."
The patent application was filed on Feb. 12, 2009 (12/370,488). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,932.PN.&OS=PN/8,164,932&RS=PN/8,164,932
Written by Shabnam Sheikh; edited by Jaya Anand.
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Advanced Ion Beam Technology Assigned Patent
ALEXANDRIA, Va., April 27 -- Advanced Ion Beam Technology, San Jose, Calif., has been assigned a patent (8,164,879) developed by five co-inventors for a step down dechucking. The co-inventors are Terry Sheng, Saratoga, Calif., Peter Mok, Fremont, Calif., Jason Hong, San Jose, Calif., Steven Fong, San Jose, Calif., and Gongyuan Qu, San Jose, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and an apparatus for dechucking an electrostatic chuck are disclosed. The gas escapes through an opening between a wafer and a chuck in each stage of a multi-stages process. In each stage, during at least a portion of the stage, the chucking voltage is reduced to a value less than the least threshold voltage needed for holding the wafer, so that the wafer is pushed away from the chuck by the gas. Hence, the gas can escape from an opening between the wafer and the chuck, thereby increasing the dechucking rate. By controlling the decrement and/or the duration of the reduced voltage, any potential damages due to the pushed-away wafer can be minimized."
The patent application was filed on April 2, 2009 (12/417,625). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,879.PN.&OS=PN/8,164,879&RS=PN/8,164,879
Written by Shabnam Sheikh; edited by Jaya Anand.
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Headway Technologies Assigned Patent
ALEXANDRIA, Va., April 27 -- Headway Technologies, Milpitas, Calif., has been assigned a patent (8,164,862) developed by four co-inventors for a "seed layer for TMR or CPP-GMR sensor." The co-inventors are Kunliang Zhang, Fremont, Calif., Tong Zhao, Fremont, Calif., Hui-Chuan Wang, Pleasanton, Calif., and Min Li, Dublin, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A composite seed layer that reduces the shield to shield distance in a read head while improving Hex (exchange coupling field) and Hex/Hc (Hc=coercivity) is disclosed and has a SM/A/SM/B configuration in which the SM layers are soft magnetic layers, the A (amorphous) layer is made of at least one of Co, Fe, Ni, and includes one or more amorphous elements, and the B layer is a buffer layer that contacts the AFM (anti-ferromagnetic) layer in the spin valve. The SM/A/SM stack together with the S1 (bottom) shield forms an effective shield such that the buffer layer serves as the effective seed layer while maintaining a blocking temperature of 260.degree. C. in the AFM layer. The lower SM layer may be omitted. Examples of the amorphous layer are CoFeB, CoFeZr, CoFeNb, CoFeHf, CoFeNiZr, CoFeNiHf, and CoFeNiNbZr while the buffer layer may be Cu, Ru, Cr, Al, or NiFeCr."
The patent application was filed on April 2, 2008 (12/080,277). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,862.PN.&OS=PN/8,164,862&RS=PN/8,164,862
Written by Shabnam Sheikh; edited by Jaya Anand.
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Goldeneye Assigned Patent
ALEXANDRIA, Va., April 27 -- Goldeneye, San Diego, has been assigned a patent (8,163,582) developed by Scott M. Zimmerman, Basking Ridge, N.J., Karl W. Beeson, Princeton, N.J., and William R. Livesay, San Diego, for a "method for fabricating a light emitting diode chip including etching by a laser beam."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for fabricating substrate-free LED chips has a multilayer semiconductor structure at least 10 microns thick provided on a growth substrate. One or more arrays of parallel streets are etched into the multilayer semiconductor structure using a first pulsed laser beam. By scanning a second pulsed laser beam through the growth substrate to the multilayer semiconductor structure, the LED chips are detached from the growth substrate while simultaneously forming surface features on the chips."
The patent application was filed on April 22, 2008 (12/148,894). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,582.PN.&OS=PN/8,163,582&RS=PN/8,163,582
Written by Shabnam Sheikh; edited by Jaya Anand.
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Hamilton Sundstrand Assigned Patent
ALEXANDRIA, Va., April 27 -- Hamilton Sundstrand, Windsor Locks, Conn., has been assigned a patent (8,164,866) developed by Sastry V. Vedula, Loves Park, Ill., Mario R. Rinaldi, Waukesha, Wis., and Kenneth Whalen, Moorpark, Calif., for an "identification and protection of an aerospace AC-DC power system in the presence of DC content due to faulty loads."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A fault protection system for an AC-DC distribution system detects the presence of DC content at individual loads, isolates the load responsible for the fault from the remainder of the distribution system, and blocks DC content from being propagated from the faulty load to the AC source. The fault protection system includes at least one circuit breaker connected to monitor the AC current provided to the individual electrical load and to detect the presence of DC content indicative of the load being faulty. In response to detected DC content, the circuit breaker trips open to disconnect the electrical load from the AC distribution system to prevent DC content from being propagated to adjacent loads."
The patent application was filed on Feb. 18, 2009 (12/388,297). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,866.PN.&OS=PN/8,164,866&RS=PN/8,164,866
Written by Shabnam Sheikh; edited by Jaya Anand.
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Western Digital Technologies Assigned Patent for Information Storage Device
ALEXANDRIA, Va., April 27 -- Western Digital Technologies, Irvine, Calif., has been assigned a patent (8,164,849) developed by Wally Szeremeta, Mission Viejo, Calif., and Bruce A. Cariker, Diamond Bar, Calif., for an "information storage device with a conductive shield having free and forced heat convection configurations."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A novel information storage device has a disk drive, a disk drive support structure adapted to maintain the disk drive base in a substantially vertical position, and an electrically conductive shield attached to the disk drive base. The electrically conductive shield is disposed adjacent and overlying the disk drive printed circuit board. The electrically conductive shield includes a fan mounting surface having a fan duct opening disposed adjacent an upper end of the electrically conductive shield, and a lower air inlet opening disposed adjacent a lower end of the electrically conductive shield. The information storage device includes no fan and no fan is attached to the fan mounting surface. The electrically conductive shield forms a continuous internal air passageway from the lower air inlet opening to the fan duct opening."
The patent application was filed on Aug. 29, 2008 (12/201,460). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,849.PN.&OS=PN/8,164,849&RS=PN/8,164,849
Written by Shabnam Sheikh; edited by Jaya Anand.
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Intermolecular Assigned Patent
ALEXANDRIA, Va., April 27 -- Intermolecular, San Jose, Calif., has been assigned a patent (8,163,631) developed by four co-inventors for "methods for discretized processing and process sequence integration of regions of a substrate." The co-inventors are Tony P. Chiang, Campbell, Calif., David E. Lazovsky, Los Gatos, Calif., Thomas R. Boussie, Santa Clara, Calif., and Alexander Gorer, Santa Clara, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention provides methods and systems for discretized, combinatorial processing of regions of a substrate such as for the discovery, implementation, optimization, and qualification of new materials, processes, and process sequence integration schemes used in integrated circuit fabrication. A substrate having an array of differentially processed regions thereon is processed by delivering materials to or modifying regions of the substrate."
The patent application was filed on Sept. 27, 2011 (13/246,045). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,631.PN.&OS=PN/8,163,631&RS=PN/8,163,631
Written by Shabnam Sheikh; edited by Jaya Anand.
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Western Digital Assigned Patent for Method and System for Providing a Write Pole
ALEXANDRIA, Va., April 27 -- Western Digital, Fremont, Calif., has been assigned a patent (8,164,855) developed by five co-inventors for a "method and system for providing a write pole in an energy assisted magnetic recording disk drive." The co-inventors are Matthew R. Gibbons, San Jose, Calif., Kroum S. Stoev, Pleasanton, Calif., Yugang Wang, Milpitas, Calif., Adam F. Torabi, Pleasanton, Calif., and Lijie Guan, San Jose, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and system for providing an energy assisted magnetic recording (EAMR) transducer coupled with a laser are described. The EAMR transducer has an air-bearing surface (ABS) residing in proximity to a media during use. The method and system include providing waveguide(s), a near-field transducer (NFT), write pole(s), and coil(s). The waveguide(s) direct energy from the laser toward the ABS. The NFT is coupled with the waveguide and focuses the energy onto the media. The write pole(s) include a stitch for providing a magnetic field to the media and a yoke coupled to the stitch. The stitch includes an ABS-facing surface, a sloped surface, and an NFT-facing surface between the ABS-facing and sloped surfaces. The NFT-facing surface is substantially parallel to the NFT. The sloped surface is sloped at least twenty-five and not more than sixty-five degrees with respect to the NFT-facing surface. The coil(s) energize the write pole(s)."
The patent application was filed on Nov. 6, 2009 (12/614,341). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,855.PN.&OS=PN/8,164,855&RS=PN/8,164,855
Written by Shabnam Sheikh; edited by Jaya Anand.
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General Photonics Assigned Patent
ALEXANDRIA, Va., April 27 -- General Photonics, Chino, Calif., has been assigned a patent (8,164,831) developed by X. Steve Yao, Diamond Bar, Calif., Jane Chen, Diamond Bar, Calif., and Yongqiang Shi, Diamond Bar, Calif., for "optical depolarizers and DGD generators based on optical delay."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques and devices for depolarizing light and producing a variable differential group delays in optical signals. In one implementation, an input optical beam is split into first and second beams with orthogonal polarizations. One or two optical reflectors are then used to cause the first and second optical beams to undergo different optical path lengths before they are recombined into a single output beam. An adjustment mechanism may used implemented to adjust the difference in the optical path lengths of the first and second beams to produce a variable DGD. When the depolarization of light is desired, the difference in the optical path lengths of the first and second beams is set to be greater than the coherence length of the input optical beam."
The patent application was filed on May 19, 2009 (12/468,801). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,831.PN.&OS=PN/8,164,831&RS=PN/8,164,831
Written by Shabnam Sheikh; edited by Jaya Anand.
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Oracle America Assigned Patent
ALEXANDRIA, Va., April 27 -- Oracle America, Redwood Shores, Calif., has been assigned a patent (8,164,918) developed by five co-inventors for a "steering fabric that facilitates reducing power use for proximity communication." The co-inventors are Alex Chow, Palo Alto, Calif., Robert J. Drost, Los Altos, Calif., Ronald Ho, Mountain View, Calif., Robert Proebsting, Sonora, Calif., and Arlene Proebsting, Sonora, Calif.,
The abstract of the patent published by the U.S. Patent and Trademark Office states: "One embodiment of the present invention provides a system that facilitates reducing the power needed for proximity communication. This system includes an integrated circuit with an array of transmission pads that transmit signals using proximity communication. This array is comprised of a set of macropads, where each given macropad is comprised of a set of micropads that can be configured to transmit a signal. A steering fabric routes signals to and within macropads, such that a subset of the micropads in the array can be configured to transmit the signal to a receiving component. Each macropad receives a limited number of input signals, with the steering fabric routing input signals to the micropads of the macropads. By limiting the number of input signals that are routed to the micropads of the macropads, the steering fabric eliminates redundant steering configurations for the array and reduces the power needed to transmit the signal."
The patent application was filed on Dec. 24, 2008 (12/317,659). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,918.PN.&OS=PN/8,164,918&RS=PN/8,164,918
Written by Shabnam Sheikh; edited by Jaya Anand.
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Alpha & Omega Semiconductor Assigned Patent
ALEXANDRIA, Va., April 27 -- Alpha & Omega Semiconductor, Sunnyvale, Calif., has been assigned a patent (8,163,601) developed by Yuping Gong, Shanghai, China, and Yan Xun Xue, Los Gatos, Calif., for a "chip-exposed semiconductor device and its packaging method."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method of making a chip-exposed semiconductor package comprising the steps of: plating a plurality of electrode on a front face of each chip on a wafer; grinding a backside of the wafer and depositing a back metal then separating each chips; mounting the chips with the plating electrodes adhering onto a front face of a plurality of paddle of a leadframe; adhering a tape on the back metal and encapsulating with a molding compound; removing the tape and sawing through the leadframe and the molding compound to form a plurality of packaged semiconductor devices."
The patent application was filed on Sept. 29, 2010 (12/894,105). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,601.PN.&OS=PN/8,163,601&RS=PN/8,163,601
Written by Shabnam Sheikh; edited by Jaya Anand.
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Oracle America Assigned Patent
ALEXANDRIA, Va., April 27 -- Oracle America, Redwood Shores, Calif., has been assigned a patent (8,164,917) developed by Jing Shi, Carlsbad, Calif., Nyles Nettleton, Cupertino, Calif., and Bruce M. Guenin, San Diego, for a "base plate for use in a multi-chip module."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A base mechanism for use in a multi-chip module (MCM) is described. This base mechanism includes a substrate having top and bottom surfaces. The bottom surface includes first electrical connectors that convey power, and through-substrate vias (TSVs) between the top and bottom surfaces are electrically coupled to these electrical connectors. Furthermore, a bridge chip is rigidly mechanically coupled to the top surface. This bridge chip includes proximity communication connectors that communicate information via proximity communication with one or more island chips in the MCM. Additionally, spacers are rigidly mechanically coupled to the top surface of the substrate. In conjunction with the bridge chip, the spacers define cavities on the top surface, which include second electrical connectors. These second electrical connectors are electrically coupled to the TSVs, and communicate additional information with and convey power to the one or more island chips."
The patent application was filed on Dec. 23, 2009 (12/646,660). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,917.PN.&OS=PN/8,164,917&RS=PN/8,164,917
Written by Shabnam Sheikh; edited by Jaya Anand.
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QUALCOMM MEMS Technologies Assigned Patent
ALEXANDRIA, Va., April 27 -- QUALCOMM MEMS Technologies, San Diego, has been assigned a patent (8,164,821) developed by Sauri Gudlavalleti, San Jose, Calif., and Clarence Chui, San Jose, Calif., for a "microelectromechanical device with thermal expansion balancing layer or stiffening layer."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An interferometric modulating device is provided with a thermal expansion balancing layer on a side of the movable flexible layer opposite the movable reflector such that when temperature changes the distance between the movable reflector and the optical stack does not change significantly, thereby leading to stable color. Additionally, an interferometric modulating device is provided with a stiffening layer between the movable flexible layer and the movable reflector and at least one hollow void exists on the surface where the movable reflector and the stiffening layer contact each other so that the movable reflector is more rigid to bending, thereby reducing the temperature sensitivity of the movable reflector."
The patent application was filed on Feb. 22, 2008 (12/072,090). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,821.PN.&OS=PN/8,164,821&RS=PN/8,164,821
Written by Shabnam Sheikh; edited by Jaya Anand.
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OC2 Technology Group Assigned Patent
ALEXANDRIA, Va., April 27 -- OC2 Technology Group, San Jose, Calif., has been assigned a patent (8,164,935) developed by Franz Michael Schuette, Colorado Springs, Colo., and William J. Allen, Cupertino, Calif., for "memory modules and methods for modifying memory subsystem performance."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods and memory modules adapted for use in computer systems to generate different voltages for core supply (VDD) and input/output supply (VDDQ) inputs to memory components of the computer memory subsystem. The memory module includes a substrate with an edge connector, a memory component, and first and second voltage planes adapted to supply the core supply voltage and the input/output supply voltage to the memory component. The first voltage plane receives a system input voltage from the edge connector, and the second voltage plane is connected to the first voltage plane to receive a second voltage that is either higher or lower than the system input voltage. One of the first and second voltage planes is connected to the memory component to supply the core supply voltage thereto, and the other voltage plane supplies the input/output supply voltage to the memory component."
The patent application was filed on Dec. 7, 2009 (12/632,176). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,935.PN.&OS=PN/8,164,935&RS=PN/8,164,935
Written by Shabnam Sheikh; edited by Jaya Anand.
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Altera Assigned Patent
ALEXANDRIA, Va., April 27 -- Altera, San Jose, Calif., has been assigned a patent (8,164,916) developed by Hong Shi, Santa Rosa, Calif., for "techniques for attenuating resonance induced impedance in integrated circuits."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Provided is an integrated circuit system and method for biasing the same that features bifurcating a power distribution network to provide a bias voltage to the integrated circuit system. One of the branches of the power distribution network attenuates an impedance in the power distribution network that supplies transient currents and the remaining branch supplies a substantially steady-state currents."
The patent application was filed on Jan. 10, 2008 (11/972,550). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,916.PN.&OS=PN/8,164,916&RS=PN/8,164,916
Written by Shabnam Sheikh; edited by Jaya Anand.
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California Institute of Technology Assigned Patent
ALEXANDRIA, Va., April 27 -- California Institute of Technology, Pasadena, Calif., has been assigned a patent (8,164,816) developed by five co-inventors for stabilizing optical resonators. The co-inventors are Anatoliy Savchenkov, Glendale, Calif., Andrey B. Matsko, Pasadena, Calif., Nan Yu, Arcadia, Calif., Lutfollah Maleki, Pasadena, Calif., and Vladimir Ilchenko, Arcadia, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Techniques and devices that stabilize optical resonators."
The patent application was filed on Sept. 2, 2008 (12/203,143). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,816.PN.&OS=PN/8,164,816&RS=PN/8,164,816
Written by Shabnam Sheikh; edited by Jaya Anand.
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Shocking Technologies Assigned Patent
ALEXANDRIA, Va., April 27 -- Shocking Technologies, San Jose, Calif., has been assigned a patent (8,163,595) developed by Lex Kosowsky, San Jose, Calif., and Robert Fleming, San Jose, Calif., for "formulations for voltage switchable dielectric materials having a stepped voltage response and methods for making the same."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Formulations for voltage switchable dielectric materials include two or more different types of semiconductive materials uniformly dispersed within a dielectric matrix material. The semiconductive materials are selected to have different bandgap energies in order to provide the voltage switchable dielectric material with a stepped voltage response. The semiconductive materials may comprise inorganic particles, organic particles, or an organic material that is soluble in, or miscible with, the dielectric matrix material. Formulations optionally can also include electrically conductive materials. At least one of the conductive or semiconductive materials in a formulation can comprise particles characterized by an aspect ratio of at least 3 or greater."
The patent application was filed on Nov. 23, 2010 (12/953,309). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,595.PN.&OS=PN/8,163,595&RS=PN/8,163,595
Written by Shabnam Sheikh; edited by Jaya Anand.
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Avalanche Technology Assigned Patent for Low Current Switching Magnetic Tunnel Junction Design
ALEXANDRIA, Va., April 27 -- Avalanche Technology, Fremont, Calif., has been assigned a patent (8,164,947) developed by Rajiv Yadav Ranjan, San Jose, Calif., Roger Klaus Malmhall, San Jose, Calif., and Parviz Keshtbod, Los Altos Hills, Calif., for a "low current switching magnetic tunnel junction design for magnetic memory using domain wall motion."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall."
The patent application was filed on Jan. 5, 2011 (12/985,028). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,947.PN.&OS=PN/8,164,947&RS=PN/8,164,947
Written by Shabnam Sheikh; edited by Jaya Anand.
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Soladigm Assigned Patent
ALEXANDRIA, Va., April 27 -- Soladigm, Milpitas, Calif., has been assigned a patent (8,164,818) developed by four co-inventors for "electrochromic window fabrication methods." The co-inventors are Mark A. Collins, Foster City, Calif., Ronald M. Parker, Bellingham, Wash., Robert T. Rozbicki, San Jose, Calif., and Dhairya Shrivastava, Los Altos, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Methods of manufacturing electrochromic windows are described. An electrochromic device is fabricated to substantially cover a glass sheet, for example float glass, and a cutting pattern is defined based on one or more low-defectivity areas in the device from which one or more electrochromic panes are cut. Laser scribes and/or bus bars may be added prior to cutting the panes or after. Edge deletion can also be performed prior to or after cutting the electrochromic panes from the glass sheet. Insulated glass units (IGUs) are fabricated from the electrochromic panes and optionally one or more of the panes of the IGU are strengthened."
The patent application was filed on Nov. 8, 2010 (12/941,882). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,818.PN.&OS=PN/8,164,818&RS=PN/8,164,818
Written by Shabnam Sheikh; edited by Jaya Anand.
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Western Digital Assigned Patent
ALEXANDRIA, Va., April 27 -- Western Digital, Fremont, Calif., has been assigned a patent (8,164,760) developed by Terrance J. Willis, Campbell, Calif., for a "method and system for interrogating the thickness of a carbon layer."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method and system for interrogating a thickness of a carbon layer are described. The carbon layer resides on at least one of a magnetic recording head and a magnetic recording disk. The method and system include providing an enhancement film on the carbon layer. The enhancement film is continuous across a portion of the carbon layer. The method and system also include exposing the enhancement film to light from a light source and detecting scattered light from the carbon layer to provide a surface enhanced Raman spectroscopy (SERS) spectrum. The enhancement film resides between the light source and the carbon layer. The method and system also include determining the thickness of the carbon layer based on the SERS spectrum."
The patent application was filed on March 11, 2010 (12/722,335). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,164,760.PN.&OS=PN/8,164,760&RS=PN/8,164,760
Written by Shabnam Sheikh; edited by Jaya Anand.
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AltaSens Assigned Patent
ALEXANDRIA, Va., April 27 -- AltaSens, Westlake Village, Calif., has been assigned a patent (8,164,657) developed by Laurent Blanquart, Westlake Village, Calif., for a "pixel or column fixed pattern noise mitigation using partial or full frame correction with uniform frame rates."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Systems and methods are provided that facilitate mitigating pixel or column fixed pattern noise in a CMOS imaging System-on-Chip (iSoC) sensor. For instance, pixel or column fixed pattern noise can be recognized by gating a pixel array without firing a transfer signal (TX). Inhibiting the transfer signal can cause zero input to be provided to pixels in the pixel array; thus, the sampled output from the pixels under such conditions can be a function of noise. Calibration and correction can thereafter be effectuated. Moreover, uniform frame rates for outputted frames can be yielded irrespective of use of a subset of read out frames for calibration. For example, frames employed for calibration can be replaced in a sequence of outputted frames by copies of stored frames. Further, signal levels can be balanced to account for differences in light integration time, which can result from blocking and unblocking firing of transfer signals."
The patent application was filed on June 27, 2008 (12/163,211). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,657&OS=8,164,657&RS=8,164,657
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Exedra Technology Assigned Patent
ALEXANDRIA, Va., April 27 -- Exedra Technology, Gilbert, Ariz., has been assigned a patent (8,164,618) developed by Chih-Lung Yang, Chunghua, Taiwan, and Lars Chapsky, South Pasadena, Calif., for an "implementation of MPCP MCU technology for the H.264 video standard."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A method for generating a video output signal. The method may include receiving a plurality of input video signals from each of the participants. Each of the input video signals may have a plurality of input frames. Each of the input frames may have a source slice carrying an image. Each of the input frames may be encoded using the respective reference frame at an encoding time. The method may include a step for generating the video output signal for transmission to the participants. The video output signal may comprise a plurality of output frames. A first of the output frames generally has at least a first slice having (a) a first coded portion carrying the image from a first of the participants and (b) a first unencoded portion for the image from a second of the participants. A second of the output frames generally has at least a second slice having (a) a second coded portion carrying the image from the second participant and (b) a second unencoded portion for the image from the first participant. The frames of the video output signal are generated as soon as one of the frames of the video input signal are received."
The patent application was filed on Feb. 13, 2009 (12/370,713). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,618&OS=8,164,618&RS=8,164,618
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Google Assigned Patent
ALEXANDRIA, Va., April 27 -- Google, Mountain View, Calif., has been assigned a patent (8,164,599) developed by Mohammed Waleed Kadous, Sunnyvale, Calif., and Russell Heywood, Santa Clara, Calif., for "systems and methods for collecting and providing map images."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "Aspects of the present disclosure relate to collecting images of maps at plurality of client devices, orienting the images with respect to the Earth, and providing the oriented maps to users. The map images may be collected by users who orient the maps by arranging the position of the image over a picture of the Earth. In another example, users may orient the maps by using "pushpins" to indicate the location of two or more points in the map image to two or more locations on the image of the Earth. The images may be processed in order to generate high quality images which may then be downloaded and used by other users."
The patent application was filed on June 1, 2011 (13/150,478). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,599&OS=8,164,599&RS=8,164,599
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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CSR Technology, Panasonic Assigned Patent
ALEXANDRIA, Va., April 27 -- CSR Technology, San Jose, Calif., and Panasonic, Osaka, Japan, have been assigned a patent (8,164,516) developed by five co-inventors for a "GPS-based positioning system for mobile GPS terminals." The co-inventors are Ikuo Tsujimoto, Nara, Japan, Junichi Suzuki, Osaka, Japan, Chiayee Steve Chang, San Jose, Calif., Lionel Jacques Garin, Palo Alto, Calif., and Ashutosh Pande, Milpitas, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention discloses a GPS system that uses call-processor intelligence to determine the mode of operation of a GPS receiver located in a GPS terminal. The modes are selected based on the availability of network facilities, the GPS information that can be acquired, or user input requirements."
The patent application was filed on Feb. 18, 2008 (12/033,000). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,516&OS=8,164,516&RS=8,164,516
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Broadcom Assigned Patent
ALEXANDRIA, Va., April 27 -- Broadcom, Irvine, Calif., has been assigned a patent (8,164,601) developed by five co-inventors for "graphics display system with anti-flutter filtering and vertical scaling feature." The co-inventors are Alexander G. MacInnis, Los Altos, Calif., Chengfuh Jeffrey Tang, Saratoga, Calif., Xiaodong Xie, San Jose, Calif., James T. Patterson, Saratoga, Calif., and Greg A. Kranawetter, San Jose, Calif.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A graphics integrated circuit chip is used in a set-top box for controlling a television display. The graphics chip processes analog video input, digital video input, and graphics input. The chip includes a single polyphase filter that preferably provides both anti-flutter filtering and scaling of graphics. Anti-flutter filtering may help reduce display flicker due to the interlaced nature of television displays. The scaling of graphics may be used to convert the normally square pixel aspect ratio of graphics to the normally rectangular pixel aspect ratio of video."
The patent application was filed on Nov. 23, 2010 (12/953,168). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,601&OS=8,164,601&RS=8,164,601
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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U.S. Navy Assigned Patent for Conversion of an Antenna to Multiband using Current Probes
ALEXANDRIA, Va., April 27 -- The U.S. Navy has been assigned a patent (8,164,534) developed by Daniel W.S. Tam, San Diego, for a "conversion of an antenna to multiband using current probes."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A multi-band antenna comprising a conductive structure and a plurality of current probes coupled around the conductive structure is disclosed. An existing antenna capable of generating H fields having a first signal line is converted into a multi-signal line antenna with increased frequency capabilities, by mounting a first current probe having a designated frequency range about a periphery of the existing antenna; coupling a second signal line to the first current probe; and performing at least one of transmitting and receiving via at least one of the first and second signal lines, wherein the mounting of the first current probe to the existing antenna improves a voltage standing wave ratio (VSWR) of the existing antenna and the second signal line operates as an independent signal line for signal reception/transmission within the designated frequency range."
The patent application was filed on March 17, 2009 (12/405,508). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,534&OS=8,164,534&RS=8,164,534
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Philips Lumileds Lighting Assigned Patent
ALEXANDRIA, Va., April 27 -- Philips Lumileds Lighting, San Jose, Calif., has been assigned a patent (8,163,575) developed by Jonathan J. Wierer Jr., Fremont, Calif., Michael R. Krames, Mountain View, Calif., and Nathan F. Gardner, Sunnyvale, Calif., for "grown photonic crystals in semiconductor light emitting devices."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A photonic crystal is grown within a semiconductor structure, such as a III-nitride structure, which includes a light emitting region disposed between an n-type region and a p-type region. The photonic crystal may be multiple regions of semiconductor material separated by a material having a different refractive index than the semiconductor material. For example, the photonic crystal may be posts of semiconductor material grown in the structure and separated by air gaps or regions of masking material. Growing the photonic crystal, rather than etching a photonic crystal into an already-grown semiconductor layer, avoids damage caused by etching which may reduce efficiency, and provides uninterrupted, planar surfaces on which to form electric contacts."
The patent application was filed on June 17, 2005 (11/156,105). The full-text of the patent can be found at http://patft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO1&Sect2=HITOFF&d=PALL&p=1&u=%2Fnetahtml%2FPTO%2Fsrchnum.htm&r=1&f=G&l=50&s1=8,163,575.PN.&OS=PN/8,163,575&RS=PN/8,163,575
Written by Shabnam Sheikh; edited by Jaya Anand.
***
OmniVision Technologies Assigned Patent
ALEXANDRIA, Va., April 27 -- OmniVision Technologies, Santa Clara, Calif., has been assigned a patent (8,164,723) developed by Matthew F. Bone, Fremont, Calif., and Justin John Skaife, Earleville, Md., for a "liquid crystal display having a thin gasket and method for manufacturing the same."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A liquid crystal display device includes a substrate, a liquid crystal layer, a liquid crystal alignment layer between the substrate and the liquid crystal layer, a barrier layer between the liquid crystal alignment layer and the liquid crystal layer, and a gasket formed around the perimeter of the liquid crystal layer and abutting the barrier layer. The gasket has a width less than or equal to 400 micrometers. A second substrate also includes a liquid crystal alignment layer and a barrier layer formed over the liquid crystal alignment layer. The gasket also abuts the barrier layer of the second substrate. In a particular embodiment, the substrate is a reflective display backplane, and the second substrate is a transparent substrate having a transparent electrode layer. The gasket of the present invention is much narrower than gaskets of the prior art, which enables LCD devices to be made smaller and cheaper because more LCD devices can be produced per wafer."
The patent application was filed on April 16, 2007 (11/787,427). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,723&OS=8,164,723&RS=8,164,723
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Rockstar Bidco Assigned Patent
ALEXANDRIA, Va., April 27 -- Rockstar Bidco, New York, has been assigned a patent (8,164,615) developed by Dany Sylvain, Gatineau, Calif., for a personalized conference bridge.
The abstract of the patent published by the U.S. Patent and Trademark Office states: "The present invention allows a user to customize her personal conference bridge such that conference participants who connect to the bridge are provided conference information selected by the user. In particular, after each conference participant gains access to the personal conference bridge, the conference information is delivered to a terminal of the conference participant. Although the user associated with the personal conference bridge may be a conference participant, delivery of conference information to the user is optional. The conference information may be any type of media content, or information identifying the location of media content to present to the conference participants."
The patent application was filed on Dec. 22, 2006 (11/615,387). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,615&OS=8,164,615&RS=8,164,615
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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BAE Systems Assigned Patent for Proper Frequency Planning in a Synthetic Instrument RF System
ALEXANDRIA, Va., April 27 -- BAE Systems, Arlington, Va., has been assigned a patent (8,164,498) developed by Anthony J. Estrada, San Diego, for a "proper frequency planning in a synthetic instrument RF system."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "A system and method for clocking in analog-to-digital (ADC) converter in a synthetic instrument unit is presented. A method begins by applying an input clock to an amplifier to produce an amplified clock. The amplified clock is filtered to produce a filtered clock. The ADC of this synthetic instrument unit is clocked with the filtered clock. The input frequency of the ADC corresponds to a second or higher order Nyquist zone that is above the sampling frequency of the ADC. The input data is carried by an intermediate frequency (IF) signal. The filtered clock of ADC is switched off a clock path of the ADC when the ADC is not in use."
The patent application was filed on Sept. 10, 2010 (12/879,666). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,498&OS=8,164,498&RS=8,164,498
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Teledyne Scientific & Imaging Assigned Patent
ALEXANDRIA, Va., April 27 -- Teledyne Scientific & Imaging, Thousand Oaks, Calif., has been assigned a patent (8,164,588) developed by Stefan Clemens Lauxtermann, Camarillo, Calif., and Hakan Durmus, Los Angeles, for a "system and method for MEMS array actuation including a charge integration circuit to modulate the charge on a variable gap capacitor during an actuation cycle."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "An actuator and method for MEMS array actuation is disclosed. In one embodiment, the actuator having a pixel coupled to a charge integration circuit, the pixel comprising a voltage bias, a variable gap capacitor, and a switch, all in series, the charge integration circuit configured to modulate charge on the variable gap capacitor during an actuation cycle. In one embodiment, the MEMS actuator having a unit cell with parasitic capacitance and coupled to a negative feedback sampling circuit, the unit cell comprising a variable gap capacitor, a voltage bias, a modulated current source, and a voltage-to-current converter, the negative feedback sampling circuit configured to receive an output current from the unit cell, convert the output current from the unit cell to a low voltage signal, sample the low voltage signal, and provide a feedback signal to the modulated current source to compensate for the parasitic capacitance in the unit cell."
The patent application was filed on May 23, 2008 (12/126,698). The full-text of the patent can be found at http://patft.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&Sect2=HITOFF&p=1&u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&r=1&f=G&l=50&co1=AND&d=PTXT&s1=8,164,588&OS=8,164,588&RS=8,164,588
Written by Satyaban Rath; edited by Hemanta Panigrahi.
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Intersil Americas Assigned Patent for Integrated Non-linearity (INL) and Differential Non-linearity (DNL) Correction Techniques for Digital-to-analog Converters (DACS)
ALEXANDRIA, Va., April 27 -- Intersil Americas, Milpitas, Calif., has been assigned a patent (8,164,495) developed by Iskender Agi, Redwood City, Calif., for an "integrated non-linearity (INL) and differential non-linearity (DNL) correction techniques for digital-to-analog converters (DACS)."
The abstract of the patent published by the U.S. Patent and Trademark Office states: "INL values are determined for a plurality of sub-segments of a DAC that is adapted to accept N bit digital input codes, and a first set of correction codes that can be used to reduce to a range of INL values (to thereby improve linearity of the DAC) are determined and stored. Additionally, DNL values are determined for the plurality of sub-segments for which INL values were determined, and a second set of correction codes that can be used to ensure that all values of DNL>-1 (to thereby ensure that the DAC is monotonic) are determined and stored. This can include using one or more extra bits of resolution to remap at least some of the 2^N possible dig
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